View AU1500_140874.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www..com
AMD AlchemyTMAU1500TM Processor Data Book
March 2006
Publication ID: 30361D
AMD AlchemyTM AU1500TM Processor Data Book
www..com
(c) 2006 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks AMD, the AMD Arrow logo, and combinations thereof, and AMD Alchemy and Au1550 are trademarks of Advanced Micro Devices, Inc. MIPS32 is a trademark of MIPS Technologies, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and/or other jurisdictions. SafeNet and CGX are trademarks of SafeNet, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
2
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Contents 30361D
Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 1.2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MIPS32TM Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Coprocessor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 System Bus (SBUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.0
Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 3.2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Static Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.0
PCI 2.2 Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.1 4.2 4.3 PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Implementation Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.0
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1 5.2 5.3 DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Using GPIO as External DMA Requests (DMA_REQn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.0
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1 6.2 6.3 6.4 Interrupt Controller Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
AMD AlchemyTM AU1500TM Processor Data Book
3
www..com
30361D Contents
7.0
Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1 7.2 7.3 7.4 7.5 7.6 AC97 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 USB Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Ethernet MAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UART Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Secondary General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.0
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.1 8.2 8.3 8.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Time of Year Clock and Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Primary General Purpose I/O and Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.0
Power-up, Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
9.1 9.2 9.3 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
10.0 EJTAG Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
10.1 10.2 10.3 10.4 EJTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Coprocessor 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 EJTAG Memory Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
11.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.0 Electrical and Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Power-up and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Asynchronous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 External Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
13.0 Packaging, Pin Assignments, and Ordering Information . . . . . . . . . . . . . . . . . 237
13.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 13.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
4
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Contents 30361D
Appendix A
A.1 A.2 A.3 A.4
Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Data Book Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Differences between AU1500TM and Au1000TM Processors . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
AMD AlchemyTM AU1500TM Processor Data Book
5
www..com
30361D Contents
6
AMD AlchemyTM AU1500TM Processor Data Book
www..com
List of Figures 30361D
List of Figures
Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21. Figure 3-22. Figure 3-23. Figure 6-1. Figure 7-1. Figure 7-2. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 8-6. Figure 8-7. Figure 9-1. Figure 9-2. Figure 9-3. Figure 11-1. Figure 12-1. Figure 12-2. Figure 12-3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Au1 Core Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Au1 Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SBUS Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SDRAM Typical Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SDRAM Typical Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SDRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Static Memory Read Timing (Single Read Followed by Burst) . . . . . . . . . . . . . . . . . . . . . . . 61 Static Memory Read EWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Static Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Static Memory Write EWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 One Card PCMCIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Two Card PCMCIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PCMCIA Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PCMCIA Memory Read PWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PCMCIA Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PCMCIA Memory Write PWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PCMCIA I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PCMCIA I/O Read PWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PCMCIA I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PCMCIA I/O Write PWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 LCD Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LCD Read LWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LCD Write LWAIT# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16-Bit Chip Select Little-Endian Data Format (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Big-Endian Au1 Core and Little-Endian 16-Bit Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Big-Endian Au1 Core and Big-Endian 16-Bit Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Interrupt Controller Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Endpoint Configuration Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Logic for Interrupt Source Number 31 on Interrupt Controller 1 . . . . . . . . . . . . . . . . . . . . . . 151 Clocking Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Frequency Generator and Clock Source Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Frequency Generator and Clock Source Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 TOY and RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 GPIO Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Sleep and Idle Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Sleep Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Hardware Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Runtime Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Voltage Undershoot Tolerances for Input and I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Voltage Overshoot Tolerances for Input and I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SDRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
AMD AlchemyTM AU1500TM Processor Data Book
7
www..com
30361D List of Figures
Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 12-13. Figure 12-14. Figure 13-1. Figure 13-2. Figure 13-3.
Static RAM, I/O Device and Flash Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PCMCIA Host Adapter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 GPIO Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Ethernet MII Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 AC-Link Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 EJTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Hardware Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Runtime Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Connection Diagram--Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 OPN Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8
AMD AlchemyTM AU1500TM Processor Data Book
www..com
List of Tables 30361D
List of Tables
Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 5-1. Table 5-2. Table 5-3. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 7-9. Table 7-10. Cache Line Allocation Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Cache Coherency Attributes (CCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Values for Page Size and PageMask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Cause[ExcCode] Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CPU Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Coprocessor 0 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Controller Block Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SDRAM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SDRAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Static Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Device Type Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Burst Size Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Actual Number of Clocks for Timing Parameters (Except Tcsh) . . . . . . . . . . . . . . . . . . . . . . 56 Actual Number of Clocks for Tcsh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Static RAM, I/O Device and Flash Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PCMCIA Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PCMCIA Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LCD Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PCI Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PCI Arbiter Priority Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PCI Error Conditions on pci_config[27:24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Data Bus Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Swapping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Supported Endian/Swapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PCI Bus Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DMA Channel Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DMA Channel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Peripheral Addresses and Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Controller Connections to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Interrupt Controller Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Interrupt Configuration Register Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 AC97 Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 AC97 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 AC-Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 USB Host Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 USB Host Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 USB Device Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 USB Device Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Endpoint Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Example Endpoint Configuration Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 USB Device Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
AMD AlchemyTM AU1500TM Processor Data Book
9
www..com
30361D List of Tables
Table 7-11. Table 7-12. Table 7-13. Table 7-14. Table 7-15. Table 7-16. Table 7-17. Table 7-18. Table 7-19. Table 7-20. Table 7-21. Table 7-22. Table 7-23. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 9-1. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 11-1. Table 11-2. Table 11-3. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 12-5. Table 12-6. Table 12-7. Table 12-8. Table 12-9. Table 12-10. Table 12-11. Table 12-12. Table 12-13. Table 12-14. Table 12-15. Table 12-16. Table 12-17. Table 12-18. Table 12-19. Table 12-20. Table 12-21. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table A-1. Table A-2.
Ethernet Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MAC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MAC DMA Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 MAC DMA Receive Entry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 MAC DMA Transmit Entry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 MAC DMA Block Indexed Address Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 UART Register Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Interrupt Cause Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 UART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 GPIO2 Register Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 GPIO2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 System Control Block Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Clock Generation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Clock Mux Input Select Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Programmable Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Peripheral Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 ROMSEL and ROMSIZE Boot Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Coprocessor 0 Registers for EJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 EJTAG Memory Mapped Registers at 0xFF300000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 EJTAG Instruction Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 EJTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Signal Type Abbreviations for Table 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Signal State Abbreviations for Table 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Thermal Characteristics with Changing Air Flow Conditions . . . . . . . . . . . . . . . . . . . . . . . . 217 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Voltage and Power Parameters for 333 MHz Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Voltage and Power Parameters for 400 MHz Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Voltage and Power Parameters for 500 MHz Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SDRAM Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Static RAM, I/O Device and Flash Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PCMCIA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 LCD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PCI Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 GPIO Timing for Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Ethernet MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 AC-Link Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 EJTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Power-up Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Hardware Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Runtime Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 External Clock EXTCLK[1:0] Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 32.768 KHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Pin Assignment -- Sorted by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Pin Assignment -- Sorted Alphabetically by Default Signal . . . . . . . . . . . . . . . . . . . . . . . . 248 Pin Assignment -- Alternate Signals Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . 253 Valid OPN Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Basic AU1500TM Processor Physical Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 255 System Bus Devices Physical Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
10
AMD AlchemyTM AU1500TM Processor Data Book
www..com
List of Tables 30361D
Table A-3. Table A-4. Table A-5. Table A-6.
Peripheral Bus Devices Physical Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Edits to Current Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
AMD AlchemyTM AU1500TM Processor Data Book
11
www..com
30361D List of Tables
12
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Overview 30361D
1.0Overview
The AMD AlchemyTM AU1500TM processor is a high-performance, low-power, high integration system-on-a-chip (SOC) designed for use in the Internet edge device market. These devices are customer premise equipment products, including both wireless and wired Internet access devices and portable compute devices, as well as Internet infrastructure products such as routers and line cards. Devices based on the AU1500 are capable of processing high performance digital video and data streams in either battery or line-powered environments. The AU1500 processor contains a PCI controller, providing a flexible interface to external peripherals.
1
1.1
Product Description
The AU1500 processor is a complete SOC based on the MIPS32TM instruction set. Designed for maximum performance at low power, the processor runs up to 500 MHz. Power dissipation is less than 700 mW for the 400 MHz version. Highly integrated with on-chip memory controllers and Internet access peripherals, the AU1500 processor runs a variety of operating systems, including Windows(R) CE, Linux, and VxWorks. Moreover, the integration of peripherals with the unique, high performance, MIPS-compatible core provides low system cost, small form factor, low system power requirement, simple designs at multiple performance points and thus, short design cycles.
SDRAM SDRAM Controller System Bus (SBUS) Enhanced MIPS32TM CPU Core 32x16 MAC Flash SRAM Controller SRAM 16 KB Inst. Cache Bus Unit 16 KB Data Cache
32-bit PCI 2.2 Interface EJTAG DMA Controller Ethernet MAC Ethernet MAC USB 1.1 Host
LCD Controller PCMCIA
ROM Expansion Bus
Power Mgmt RTC (2) USB 1.1 Device AC97 Controller Peripheral Bus
Interrupt Controller GPIO (39) UART (2)
Figure 1-1. Block Diagram
AMD AlchemyTM AU1500TM Processor Data Book
13
www..com
30361D Overview
1.2
Features
Write-back with read-allocate Cache Management Features:
High Speed MIPS CPU Core
333, 400, or 500 MHz MIPS32 instruction set 32-bit architecture 16 KB instruction and 16 KB data caches High speed multiply-accumulate (MAC) and divide unit 1.5V core @ 333 MHz and 400 MHz,
-- Programmable allocation policy -- Line locking
Prefetch instructions (instruction and data) High speed access to on-chip buses
1.8V core @ 500 MHz
3.3V I/O Pipeline:
MMU
Instruction and data watch registers for software break-
points
Separate interrupt exception vector TLB Features:
-- Scalar 5-stage pipeline -- Load/store adder in I-stage (instr decode) -- Scalar branch techniques optimized: Pipelined register file access in fetch stage -- Zero penalty branch
Multiply-Accumulate (MAC) and Divide Unit:
-- 32 dual-entry fully-associative -- Variable page sizes: 4 KB to 16 MB -- 4-entry ITB Low System Power
Core / Power:
-- Max issue rate of one 32x16 MAC per clock -- Max issue rate of one 32x32 MAC per every other clock -- Operates in parallel to CPU pipeline -- Executes all integer multiply and divide instructions -- 32 x 16-bit MAC hardware
-- 333 MHz / 400 mW -- 400 MHz/ 700 mW -- 500 MHz/ 1.2 W
Power-Saving Modes:
Highly-Integrated System Peripherals
GPIOs (39 total, 22 dedicated for system use) Two 10/100 Ethernet MAC controllers USB 1.1 device and host controllers Two UARTs AC97 controller PCI interface PCMCIA interface
-- Idle -- Sleep
Pseudo-static design to 0 Hz
Package
424 BGA (Ball Grid Array), 19x19 mm
Operating System Support
Microsoft(R) Windows(R) CE Linux VxWorks
High-Bandwidth Memory Buses
100 MHz SDRAM controller (@400 MHz) SRAM/Flash EPROM controller
Development Tool Support
Complete MIPS32TM Compatible Tool Set Numerous 3rd-Party Compilers, Assemblers and
Debuggers Caches
16 KB non-blocking data cache 16 KB instruction cache Instruction and data caches are 4-way
set associative
14
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.0CPU
The AU1500 CPU core is a unique implementation of the MIPS32 instruction set architecture (ISA) designed for high frequency and low power. This chapter provides information on the implementation details of this MIPS32 compliant core. The full description of the MIPS32 architecture is provided in the "MIPS32TM Architecture For Programmers" documentation, available from MIPS Technologies, Inc. The information contained in this chapter supplements the MIPS32 architecture documentation.
2
2.1
Core
The AU1500 CPU core (Au1) is a high performance, low power implementation of the MIPS32 architecture. Figure 2-1 shows a block diagram of the core.
mini-ITLB EJTAG Instruction Cache CP0 Registers
Register File Fetch Decode Execute Cache Writeback Miss SBUS Interface Hit SBUS Data Cache Write Buffer
MAC
TLB
Figure 2-1. Au1 Core Diagram
AMD AlchemyTM AU1500TM Processor Data Book
15
www..com
30361D CPU
The Au1 core contains a five-stage pipeline. All stages complete in a single cycle when data is present. All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs. The general purpose register file has two read ports and one write port. The write port is shared with data cache loads and the pipeline Writeback stage.
2.1.1
Fetch Stage
The Fetch stage retrieves the next instruction from the instruction cache, where it is passed to the Decode stage. If the instruction is not present in the instruction cache, then the fetch address is forwarded to the virtual memory unit in order to fulfill the request. Instruction fetch stalls until the next instruction is available.
2.1.2
Decode Stage
The Decode stage prepares the pipeline for executing the instruction. In the Decode stage, the following occur in parallel: * The instruction is decoded. * Control for the instruction is generated. * Register data is read. * The branch target address is generated. * The load/store address is generated. Instructions stall in the Decode stage if dependent data or resources are not yet available. At the end of the Decode stage a new program counter value is sent to the Fetch stage for the next instruction fetch cycle.
2.1.3
Execute Stage
In the Execute stage, instructions that do not access memory are processed in hardware (shifters, adders, logical, comparators, etc.). Most instructions complete in a single cycle, but a few require multiple cycles (CLO, CLZ, MUL). The virtual address calculation begins in the Decode stage so that physical address calculation can complete in the Execute stage, in time to initiate the access to the data cache in the Execute stage. If the physical address misses in the TLB, a TLB exception is posted. Multiplies and divides are forwarded to the Multiply Accumulate unit. These instructions require multiple cycles to execute and operate mostly independent of the main five-stage pipeline. All exception conditions (arithmetic, TLB, interrupt, etc.) are posted by the end of the Execute stage so that exceptions can be signalled in the Cache stage.
2.1.4
Cache Stage
In the Cache stage, load and store accesses complete. Loads that hit in the data cache obtain the data in the Cache stage. If a load misses in the data cache, or is to a non-cacheable location, then the request is sent to the System Bus (SBUS) to be fulfilled. Load data is forwarded to dependent instructions in the pipeline. Stores that hit in the data cache are written into the cache array. If a store misses in the data cache, or is to a non-cacheable location, then the store is sent to the write buffer. If any exceptions are posted, an exception is signaled and the Au1 core is directed to fetch instructions at the appropriate exception vector address.
2.1.5
Writeback Stage
In the Writeback stage, results are posted to the general purpose register file, and forwarded to other stages as needed.
16
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.1.6
Multiply Accumulate Unit
The Multiply Accumulate unit (MAC) executes all multiply and divide instructions. The MAC is composed of a 32x16 bit pipelined array multiplier that supports early out detection, divide block, and the HI and LO registers used in calculations. The MAC operates in parallel with the main five-stage pipeline. Instructions in the main pipeline that do not have dependencies on the MAC calculations execute simultaneously with instructions in the MAC unit. A multiply calculation of 16x16 or 32x16 bits can complete in one cycle. The 32x16 bit multiply must have the signextended 16-bit value in register operand rt of the instruction. 32x32 bit multiplies may be started every other CPU cycle. The 32x32 multiplies will complete in two cycles if the results are written to the general purpose registers. If the results are written to the HI/LO registers then three cycles are required for 16x16 and 32x16 bit multiplies. 32x32 bit multiplies that use HI/LO will complete in four cycles. Divide instructions complete in a maximum of 35 cycles.
2.2
Caches
The Au1 core contains independent, on-chip 16KB instruction and data caches. As shown in Figure 2-2, each cache contains 128 sets and is four-way set associative with 32 bytes per way (cache line).
128 Sets Way 0 Way 1 Way 2 Way 3
Address Tag & State Address Tag & State Address Tag & State Address Tag & State
Word 0 Word 0 Word 0 Word 0
Word 1 Word 1 Word 1 Word 1
Word 2 Word 2 Word 2 Word 2
Word 3 Word 3 Word 3 Word 3
Word 4 Word 4 Word 4 Word 4
Word 5 Word 5 Word 5 Word 5
Word 6 Word 6 Word 6 Word 6
Word 7 Word 7 Word 7 Word 7
Figure 2-2. Cache Organization
A cache line is tagged with a 20-bit physical address, a lock bit, and a valid bit. Data cache lines also include coherency and dirty status bits. The physical address tag contains bits 31:12 of the physical address; as such, physical addresses in which bits 35:32 are non-zero must be mapped non-cacheable.
Cache Line State Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Physical Address Tag
8
7
6
5
4
3 D
2 S
1 L
0 V
A cache line address is always 32-byte aligned. The cache is indexed with the lower, untranslated bits (bits 11:5) of the virtual address, allowing the virtual-to-physical address translation and the cache access to occur in parallel.
Cache Address Decode Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Virtual/Physical Address Set Select
6
5
4
3210 Byte Select
2.2.1
Cache Line Replacement Policy
In general, the caches implement a least recently used (LRU) replacement policy. Each cache set maintains true LRU status bits (MRU, nMRU and LRU) to determine which cache line is selected for replacement. However, software can influence which cache line is replaced by marking memory pages as streaming, or by locking lines in the cache.
2.2.2
Cache Line Locking Support
The CACHE instruction is used to lock individual lines in the cache. A locked line is not subject to replacement. All four lines in a set can not be locked at once; at least one line is always available for replacement. To unlock individual cache lines use the CACHE instruction with a `hit invalidate' command opcode. See Section 2.2.5 "Cache Management" on page 19 for further discussion of the CACHE instruction.
AMD AlchemyTM AU1500TM Processor Data Book
17
www..com
30361D CPU
2.2.3
Cache Streaming Support
Streaming is typically characterized as the processing of a large amount of transient instructions and/or data. In traditional cache implementations (without explicit support for streaming), transient instructions and/or data quickly displace useful, recently used items in the cache. This yields poor utilization of the cache and results in poor system performance. The Au1 caches explicitly support streaming by placing instructions and/or data marked as streaming into way 0 of the cache. This method ensures that streaming does not purge the cache(s) of useful, recently used items, while permitting transient instructions and/or data to be cached. The CCA bits in the TLB entry indicate if a page contains streaming instructions and/or data. In addition, the PREF instruction is available to software to allow data to be placed in the data cache in advance of its use.
2.2.4
Cache Line Allocation Behavior
When an instruction fetch misses in the instruction cache, or a data load misses in the data cache, a burst fill operation is performed to fill the cache line from memory. The cache line is selected by the following algorithm: MRU is most recently used nMRU is next most recently used nLRU is next least recently used LRU is least recently used Cache Miss: if (Streaming CCA=6) then Replacement = 0, else if (LRU is !Valid or !Locked) then Replacement = LRU else if (nLRU is !Valid or !Locked) then Replacement = nLRU else if (nMRU is !Valid or !Locked) then Replacement = nMRU else Replacement = MRU Cache Hit: new MRU = Hit Way In short, the LRU selection is true LRU but with the following priorities: 1) 2) 3) Streaming: cache misses are forced to way 0. Locking: cache misses follow policy above and set Lock bit. Normal: true LRU replacement.
Table 2-1 summarizes cache line allocation for misses, as well as cache hit behavior. The table also shows how prefetching and cache locking affect the cache for hits and misses.
Table 2-1. Cache Line Allocation Behavior
Operation NORMAL Data load, Instruction fetch Data store STREAMING (CCA=6) Data load, Instruction fetch Data store PREF (data prefetch instruction with 0x4 hint) LOCKING CACHE 0x1D/0x1C (cache management instruction with Lock opcode) Set Lock bit in whichever cache line contains the address. Allocate and fill cache line; set Lock bit. Read data from whichever cache line contains the address. Write data to whichever cache line contains the address. No action taken--data remains in current cache line. Allocate and fill cache line in Way 0; maintain Lock bit; return read data. Send to the write buffer. Allocate and fill cache line in Way 0; maintain Lock bit. Read data from whichever cache line contains the address. Write data to whichever cache line contains the address. Allocate and fill cache line; clear Lock bit; return read data. Send to the write buffer. Hit Miss
18
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.2.5
Cache Management
The caches are managed with the CACHE instruction. The effect of the CACHE instruction is immediately visible to subsequent data accesses. Table 2-2 shows the cache operations, including the opcode to direct the operation to either the instruction cache or data cache. (An "n/a" indicates that the operation is not applicable.)
Table 2-2. Cache Operations
Operation Index Invalidate Index Load Tag Index Store Tag Hit Invalidate Fill Hit Writeback and Invalidate Hit Writeback Fetch and Lock CACHE[20..18] Encoding 000 001 010 100 101 101 110 111 Opcode for Instruction Cache 0x00 0x04 0x08 0x10 0x14 N/A N/A 0x1C Opcode for Data Cache 0x01 (with writeback) 0x05 0x09 0x11 N/A 0x15 0x19 0x1D
These cache operations permit initialization, locking/unlocking and management of the caches.
2.2.6
Cache Coherency Attributes (CCA)
The cache coherency attributes (CCA) field in Config0[K0] and in the TLB determine the cache-ability of accesses to memory. Cached accesses (except CCA = 4) are performed critical-word-first to improve performance. The Au1 implements the following:
Table 2-3. Cache Coherency Attributes (CCA)
CCA 0, 1 2 3 4 5 6 7 CCA (3 Bits) 00x 010 011 100 101 110 111 Description Reserved (undefined). Uncached, non-mergeable, non-gatherable. Required by the MIPS32 architecture. In addition, data is not merged within the write buffer to achieve a truly uncached effect. Cached, mergeable, gatherable. Cached, mergeable, gatherable (word 0 first). Word 0 is always accessed first; that is, the cache line is accessed in word order (word 0, 1...7). Cached, mergeable, gatherable. Cached, mergeable, gatherable, streaming. Instructions and/or data are placed into way 0. Uncached, mergeable, gatherable. Even though data is not cached, data stores sent to the write buffer are subject to merging and gathering in the write buffer.
2.2.7
Instruction Cache
The instruction cache is a 16 KB, four-way set associative cache. The instruction cache services instruction fetch requests from the Fetch stage of the pipeline. An instruction cache line state consists of a 20-bit physical address tag, a lock bit (L) and a valid bit (V).
Instruction Cache line state Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Physical Address Tag
8
7
6
5
4
3
2
1 L
0 V
AMD AlchemyTM AU1500TM Processor Data Book
19
www..com
30361D CPU
2.2.7.1 Instruction Cache Initialization and Invalidation Out of reset, all instruction cache lines are invalidated; thus the instruction cache is ready for use. To invalidate the instruction cache in software, a loop of index invalidate CACHE instructions for each of the lines in the cache invalidates the cache. li t0,(16*1024) # Cache size li t1,32 # Line size li t2,0x80000000 # First KSEG0 address addu t3,t0,t2 # terminate address of loop loop: cache 0,0(t2) # Icache indexed invalidate tag addu t2,t1 # compute next address bne t2,t3,loop nop 2.2.7.2 Instruction Cache Line Fills If an instruction fetch address hits in the instruction cache, the instruction word is returned to the Fetch stage. If the fetch address misses in the cache, and the address is cacheable, then the instruction cache performs a burst transfer from the memory subsystem to fill a cache line, and returns the instruction word to the Fetch stage. The instruction cache line is selected by the replacement policy described in Section 2.2.1 "Cache Line Replacement Policy" on page 17. 2.2.7.3 Instruction Cache Coherency The instruction cache does not maintain coherency with the data cache. Coherency between the instruction cache and the data cache is the responsibility of software. However, the data cache snoops during instruction cache line fills. Maintaining coherency is important when loading programs into memory, creating exception vector tables, or for self-modifying code. In these circumstances, memory is updated with new instructions using store instructions which places the new instructions in the data cache, but not in the instruction cache (thus the instruction cache may contain old instructions). To maintain coherency, software must use the CACHE instruction to invalidate the modified range of program addresses in the instruction cache. Because the data cache snoops during instruction cache line fills, it is not necessary to writeback the data cache prior to invalidating the instruction cache. An instruction fetch to the newly loaded/modified program correctly fetches the new instructions. 2.2.7.4 Instruction Cache Control The cache-ability of instructions is controlled by three mechanisms: * Config0[K0] field * The CCA bits in the TLB * The CACHE instruction The Config0[K0] field contains a cache coherency attribute (CCA) setting to control the cache-ability of KSEG0 region. At reset, this field defaults to CCA=3 (cacheable). The CCA bits in the TLB entry control the cache-ability of the KUSEG, KSEG2, and KSEG3 regions. Each TLB entry specifies a CCA setting for the pages mapped by the TLB. The CACHE instruction manages the caches, including the ability to lock lines in the cache. Valid instruction cache operations are the following: * Index Invalidate * Index Load Tag * Index Store Tag * Hit Invalidate * Fill * Fetch and Lock
20
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
The effect of the CACHE instruction is visible to subsequent instructions not already in the pipeline. Instructions already in the fetch and decode stages of the pipeline are not affected by a cache operation on the instruction cache.
2.2.8
Data Cache
The data cache is a 16 KB four-way set associative write-back cache. Data cache accesses are distributed across the Execute and Cache pipeline stages. A data cache line state consists the 20-bit physical address tag, a dirty bit (D), a coherency bit (S), a lock bit (L) and a valid bit (V).
Data cache line state Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Physical Address Tag
8
7
6
5
4
3 D
2 S
1 L
0 V
The data cache employs a read-allocate policy. Cache lines can be replaced on loads, but not on stores. Stores that miss in the data cache are forwarded to the write buffer. The data cache supports hit-under-miss for one outstanding miss. If an access misses in the data cache, the data cache services the next access while the memory subsystem provides the data for the missed access. If the next access hits in the data cache, the data is available immediately; otherwise the cache stalls the access until the first access completes. 2.2.8.1 Data Cache Initialization and Invalidation Out of reset, all data cache lines are invalidated; thus the data cache is ready for use. To invalidate the data cache in software, a loop of indexed writeback invalidate CACHE instructions for each of the lines in the cache invalidates the cache. li t0,(16*1024) # Cache size li t1,32 # Line size li t2,0x80000000 # First KSEG0 address addu t3,t0,t2 # terminate address of loop loop: cache 1,0(t2) # Dcache indexed invalidate tag addu t2,t1 # compute next address bne t2,t3,loop nop 2.2.8.2 Data Cache Line Fills A data cache access is initiated in the Execute stage which allows a cache hit or miss indication and all exceptions to be signaled early in the Cache stage. If the data address hits in the data cache, the data is available in the Cache stage. If the data address misses in the data cache, and the address is cacheable, the data cache performs a burst fill to a cache line, forwarding the critical word to the Cache stage. The data cache line is selected by the replacement policy described in Section 2.2.1 "Cache Line Replacement Policy" on page 17. If the line selected contains modified data (cache line is valid and has its dirty bit set by a store hit), then the cache line is moved to a cast-out buffer, the cache line is filled from memory and the load request fulfilled, and then the cast-out buffer is written to memory. 2.2.8.3 Data Cache Coherency The data cache snoops coherent SBUS transactions to maintain data coherency with other SBUS masters (i.e. DMA). If a coherent read transaction on the SBUS hits in the data cache, the data cache provides the data. If a coherent write transaction on the SBUS hits in the data cache, the data cache updates its internal array with the data. If a coherent transaction (read or write) misses in the data cache, the data cache array is unchanged by the transaction. Loads and stores which hit in the data cache can bypass previous stores in cacheable regions. The read-allocate data cache policy forwards store-misses to the write buffer. Subsequent loads and stores which hit in the data cache, and to a different cache line address than store-misses, are fulfilled immediately (while store-misses may still be in the write buffer). However, if a load address hits in a cache-line address of an item in the write buffer, the load is stalled until the write buffer commits the corresponding store. The data cache also maintains coherency with other caching masters. When a load is serviced from another caching master, both caching masters set the shared bit for the affected cache line. Then if a store occurs to a data cache line with the
AMD AlchemyTM AU1500TM Processor Data Book
21
www..com
30361D CPU
shared bit set, the cache line address is broadcast on the SBUS to invalidate cache lines in other caching masters that contain the same address. The data cache is single-ported; therefore transactions on the SBUS are prioritized over accesses by the core. However, the data cache design prevents the SBUS from saturating the data cache indefinitely, which ensures that the core can make forward progress. When changing the CCA encoding in Config0[K0] or the TLB to a different CCA encoding, software must ensure that data integrity is not compromised by first pushing modified (dirty) data to memory within the page. This is especially important when changing from a coherent CCA encoding to a non-coherent CCA encoding. 2.2.8.4 Data Cache Control The cache-ability of data accesses is controlled by four mechanisms: * Config0[K0] field * The CCA bits in the TLB * The CACHE instruction * The PREF instruction The Config0[K0] field contains a cache coherency attribute (CCA) setting to control the cache-ability of KSEG0 region. At reset, this field defaults to 011b, cacheable. The CCA bits in the TLB entry control the cache-ability of the KUSEG, KSEG2, and KSEG3 regions. Each TLB entry specifies a CCA setting for the pages mapped by the TLB. The CACHE instruction manages the caches; including the ability to lock lines in the cache. Valid data cache operations are: * Index Writeback Invalidate * Index Load Tag * Index Store Tag * Hit Invalidate (unlocks) * Hit Writeback and Invalidate * Hit Writeback * Fetch and Lock The effect of the CACHE instruction is immediately visible to subsequent data accesses. The PREF instruction places data into the data cache. The following prefetch hints are implemented: * 0x00 - Normal load * 0x04 - Streaming load The streaming load hint directs the data be placed into way 0 of the data cache (even if the line is locked), thus permitting transient data to be cached and non-transient data to remain in the cache for improved performance. Data cache streaming support combined with the PREF instruction enhances multimedia processing.
22
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.3
Write Buffer
The Au1 write buffer is depicted in Figure 2-3. All non-cacheable processor stores and data cache store-misses (the data cache is a read-allocate policy) are routed through the write buffer. Address Data Merge Latch CV 35 0 BM 31 0 Entry 15
Entry 0 SBUS (System Bus)
Figure 2-3. Au1 Write Buffer
The write buffer is a 16-word deep first-in-first-out (FIFO) queue. All processor stores arrive first at the merge latch, where merging and gathering decisions are performed, and then travel through the queue. The write buffer arbitrates for the SBUS to perform consolidated transfers to the main memory. A write buffer FIFO entry contains the address (word address), the data and associated byte masks (BM), and two control bits. The four BM bits indicate which bytes within the word contain valid data. The two control bits are the Valid bit which indicates if the entry is valid, and the Closed (C) bit. When a C bit is set, the write buffer initiates a request to the SBUS so that it can transfer data to memory. The circumstances for which the C bit is set are described below. The write buffer is capable of variable-length burst writes to memory. The length can vary from one word to eight words, and is determined by the C bits in the write buffer. During each beat of the burst, the appropriate bytes to write are selected from the corresponding byte masks. As each entry is written to memory, it is popped from the FIFO, advancing each entry in the FIFO by one. In other words, entry 0 is always presented to the SBUS for writing. When the write buffer has at least one empty entry, processor stores do not stall, thus improving processor performance. The write buffer is disabled by setting Config0[WD] to 1. In this instance, all non-cacheable and data cache store-misses stall until the write completes. The remaining description of the write buffer operation assumes Config0[WD] is 0. Out of reset, Config0[WD] is 0.
AMD AlchemyTM AU1500TM Processor Data Book
23
www..com
30361D CPU
2.3.1
Merge Latch
All processor stores first arrive at the merge latch. Logic within the merge latch decides what action to take with the incoming data. 1) 2) The incoming address is the same word address as the merge latch address. This case is for Merging, which occurs within the merge latch itself. The incoming word address is sequentially adjacent to the merge latch word address (incoming address is merge latch address + 4). This case is for Gathering. The merge latch contents are propagated to the FIFO with the C bit cleared for this entry. Neither 1 nor 2 is true. The merge latch contents are propagated to the FIFO with the C bit set for this entry.
3)
If the merge latch contents are propagated to the FIFO, the incoming address and data are placed in the merge latch for future comparisons. Furthermore, if the incoming address is the last word address of the maximum burst line size (the least significant 5 bits are 0x1C), then the C bit is set.
2.3.2
Write Buffer Merging
Write buffer merging combines stores destined for the same word address. Merging places the incoming data into the appropriate data byte(s) within the merge latch. Write buffer merging is particularly useful for sequential, incremental address write operations, such as string operations. With write buffer merging, the writes are merged into 32-bit writes which reduces the number of accesses to the memory and increases the effective throughput to main memory. This example demonstrates merging: these five byte writes occur in sequence: 0x00001000 0x00001001 0x00001002 0x00001003 0x00001002 = = = = = 0xAB 0xCD 0xDE 0xEF 0xBE
After the first four writes, the data in the merge latch contains 0xABCDDEEF. However, after the fifth write, the merge latch data now contains 0xABCDBEEF. So long as the incoming word address is the same as the merge latch word address, the data can change without a processor stall or access to memory. Write buffer merging is controlled by the Config[NM] bit and the TLB[CCA] setting. When Config0[NM] is 1 or TLB[CCA] is 2, the merge latch does not perform merging. Conversely, Config0[NM] is 0 or TLB[CCA] is not 2 enables merging. Out of reset, Config0[NM] is 0. Note: Merging takes place only in the merge latch. As such, writes to an address which are in the FIFO (but not in the merge latch) do not merge. In the example below, writes to 0x0001000 and 0x0001002 do not merge because the intervening write to address 0x00001005 is not in the same word address which caused 0x00001000 to leave the merge latch. 000 = 0xAB 005 = 0xCD 002 = 0xDE
24
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.3.3
Write Buffer Gathering
Write buffer gathering combines sequentially adjacent word addresses for burst transfers to the main memory. When a C bit is set, all queue entries from zero (0) up to and including the entry with its C bit set (N) are written to main memory in a single burst. Write buffer gathering is particularly useful for sequential, incremental address store operations, such as string operations. With write buffer gathering, the stores are combined into bursts up to 32-bytes (eight words) in length which reduces the number of accesses to the memory and increases effective throughput. Here is an example of an eight-word burst. The burst could result from code which sequentially writes words (optimized memcpy(), for example). These eight word writes occur in sequence: 0x00001000 0x00001004 0x00001008 0x0000100C 0x00001010 0x00001014 0x00001018 0x0000101C The entries corresponding to word addresses 0x00001000 through 0x00001018 have C bit set to zero. When address 0x0000101C arrives, its C bit is set. When the write buffer is granted the SBUS, it bursts all eight entries to main memory. Here is an example of two-word burst. This burst may be typical of application software. These four word writes occur in sequence: 0x00001000 0x00001004 0x0000100C 0x00001008 The C bit is cleared for the 0x00001000 entry and is set for the 0x00001004 entry. These two words are then burst to main memory. The 0x0000100C entry also has its C bit set, and is written to memory. The 0x00001008 will reside in the merge latch until displaced by a subsequent store.
2.3.4
Write Buffer Reads
When a read from memory is initiated, the read cache-line address (A35..A5) is compared against all cache-line addresses in the write buffer. If the read cache-line address matches a write buffer cache-line address, the read is stalled. The write buffer then flushes entries to memory until the read address no longer matches a write buffer cache-line address. The read is then allowed to complete. The write buffer ensures data integrity by not allowing reads to bypass writes.
2.3.5
Write Buffer Coherency
Non-cacheable stores and/or data cache store-misses reside in the write buffer, possibly indefinitely. Furthermore, the write buffer does not snoop SBUS transactions (e.g. integrated peripheral DMA engines). To ensure the write buffer contents are committed to memory, a SYNC instruction must be issued. Issuing a SYNC instruction prior to enabling each DMA transfer from memory buffers and/or structures is necessary. Without the SYNC, the DMA engine may retrieve incomplete buffers and/or structures (the remainder of which may be in the write buffer). Issuing a SYNC instruction after a store to an I/O region where stores have side effects is necessary. Without the SYNC instruction, the store may not leave the write buffer to achieve the side effects (e.g. clearing an interrupt acknowledge bit). Note that a read access does not guarantee a complete write buffer flush since the write buffer flushes as few entries as necessary until the read address no longer matches an address in the write buffer.
AMD AlchemyTM AU1500TM Processor Data Book
25
www..com
30361D CPU
2.4
Virtual Memory
The Au1 implements a TLB-based virtual address translation unit which is compliant with the MIPS32 specification. This scheme is similar to the R4000 TLB and CP0 implementation. The "MIPS32 Architecture For Programmers Volume III" contains all the information relevant to a TLB-based virtual address translation unit. The virtual address translation architecture is composed of a main 32-entry fully associative TLB array. To improve instruction fetch performance, a 4-entry fully associative instruction TLB is implemented. This miniature instruction TLB is fully coherent with the main TLB array and is completely transparent to software. Each TLB entry maps a 32-bit virtual address to a pair of 36-bit physical addresses. The page size of a TLB entry is variable under software control, from 4 KB to 16 MB. A TLB entry is described below.
TLB Entry Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 PageMask PageMask
EntryHi EntryLo0 0 EntryLo1 0
8
7
6 0
5
4
3
2
1
0
VPN2 0 0 PFN0 PFN1
0
ASID C0 C1 D0 V0 G D1 V1 G
The size of the page(s) that the TLB entry translates is determined by PageMask. The valid values for PageMask range from 4 KB to 16 MB, according to Table 2-4.
Table 2-4. Values for Page Size and PageMask Register
Page Size 4 KB 16 KB 64 KB 256 KB 1 MB 4 MB 16 MB PageMask Register 0x00000000 0x00006000 0x0001E000 0x0007E000 0x001FE000 0x007FE000 0x01FFE000 Bits [28:13] 0000000000000000 0000000000000011 0000000000001111 0000000000111111 0000000011111111 0000001111111111 0000111111111111 PFN Select Bit 12 14 16 18 20 22 24
The PageMask determines the number of significant bits in the 32-bit address generated by the program (either as a load/ store address or an instruction fetch address). The upper, significant bits of the program address are compared against the upper, significant bits of VPN2. When an address match occurs, the even/odd PFN select bit of the program address selects either PFN0 (even) or PFN1 (odd) as the upper bits of the resulting 36-bit physical address. The TLB mechanism permits mapping a larger, 36-bit physical address space into the smaller 32-bit program address space. The Au1 implements an internal 36-bit physical address SBUS which is then decoded by integrated peripherals, and by chip-selects for external memories and peripherals. The cache coherency attributes (CCA) of the physical page are controlled by the TLB entry. The valid values are described in Table 2-3 on page 19. In general, I/O spaces require a non-cacheable setting, whereas memory can utilize a cacheable setting. Note: Physical addresses in which address bits [35:32] are non-zero must be mapped non-cached (CCA = 2).
The TLB array is managed completely by software. Software can implement a TLB replacement algorithm that is either random (via the TLBWR instruction) or deterministic (via the TLBWI instruction). Hardware is available to segment the TLB via the Wired register so different replacement strategies can be used for different areas of the TLB.
26
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.5
Exceptions
The Au1 core implements a MIPS32 compliant exception scheme. The scheme consists of the exception vector entry points in both KSEG0 and KSEG1, and the exception code (ExcCode) encodings to determine the nature of the exception.
2.5.1
Exception Causes
The nature of an exception is reported in the Cause[ExcCode] field. The Au1 core can generate the following exceptions:
Table 2-5. Cause[ExcCode] Encodings
ExcCode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 23 24 Mnemonic Int Mod TLBL TLBS AdEL AdES IBE DBE Sys Bp RI CpU Ov Tr WATCH MCheck Description Interrupt TLB modification exception TLB exception (load or instruction fetch) TLB exception (store) Address error exception (load or instruction fetch) Address error exception (store) Bus error exception (instruction fetch) Bus error exception (data reference: load or store) Syscall exception Breakpoint exception Reserved instruction exception Coprocessor Unusable exception Arithmetic Overflow exception Trap exception Reference to Watchpoint address Machine Check (duplicate TLB entry)
The Au1 core does not implement hardware floating-point. As a result, all floating-point instructions generate the Reserved Instruction (RI) exception, which permits floating-point operations to be emulated in software. In addition, the Au1 core does not recognize Soft Reset, Non-Maskable Interrupt (NMI), or Cache Error exception conditions.
AMD AlchemyTM AU1500TM Processor Data Book
27
www..com
30361D CPU
2.5.2
Interrupt Architecture
The Au1 core implements a MIPS32 compliant interrupt mechanism in which eight interrupt sources are presented to the core. Each interrupt source is individually maskable to either enable or disable the core from detecting the interrupt. Interrupts are generated by software, integrated interrupt controllers, performance counters and timers, as noted in Table 2-6.
Table 2-6. CPU Interrupt Sources
Interrupt Source Software Interrupt 0 Software Interrupt 1 Interrupt Controller 0: Request 0 Request 1 Interrupt Controller 1: Request 0 Request 1 Performance Counters Count/Compare CP0 Cause Register Bit 8 9 10 11 12 13 14 15 CP0 Status Register Bit 8 9 10 11 12 13 14 15
All interrupt sources are equal in priority; that is, the interrupt sources are not prioritized in hardware. As a result, software determines the relative priority of the interrupt sources. When Cause[ExcCode]=0, software must examine the Cause[IP] bits to determine which interrupt source is requesting the interrupt. For more information on Interrupt Controller 0 and 1 see Section 6.0 "Interrupt Controller" on page 95.
2.6
MIPS32TM Instruction Set
The Au1 core implements the instruction set defined in "MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set". The floating-point instructions are not implemented in the Au1 core, but may be emulated in software. The MIPS32 ISA is characterized as a combination of the R3000 user level instructions (MIPSII) and the R4000 memory management and kernel mode instructions (32-bit MIPSIII).
2.6.1
CACHE Instruction
The CACHE instruction permits management of the Au1 instruction and data caches. The valid operations are listed in Table 2-2 "Cache Operations" on page 19. For data cache operations, the effect of the CACHE instruction is immediately visible to subsequent data accesses. However, for instruction cache operations, the effect of the CACHE instruction is not visible to subsequent instructions already in the Au1 core pipeline. Therefore, care should be exercised if modifying instruction cache lines containing the CACHE and subsequent instructions. When issuing the CACHE instruction with indexed operations (Index Invalidate, Index Load Tag and Index Store Tag) the format of the effective address is as follows:
CACHE Index Operation Address Decode Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x8000 Way
987 Set/Index
6
5
4
3210 Byte Select
The effective address base should be 0x80000000 (KSEG0) to avoid possible TLB exceptions, and place zeros in the remainder of the effective address. The format correlates to a 16KB cache that is 4-way set associative with 128 sets and 32-byte line size. Software must not use the Index Store Tag CACHE operation to change the Dirty, Lock and Shared state bits. To set the Lock bit, software must use the Fetch and Lock CACHE operation.
28
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
The Index Load Tag and Index Store Tag CACHE operations utilize CP0 registers DTag, DData, ITag and IData. The format of data for Index Tag operations is depicted in the description of these registers. CACHE operations that require an effective address (i.e., not the Index operations) do not generate the Address Error Exception or trigger data watchpoint exceptions.
2.6.2
PREF Instruction
The PREF instruction prefetches data into the data cache. Data is prefetched to improve algorithm performance by placing the data in the cache in advance of its use, thus minimizing stalls due to data cache load misses. See also Section 2.2.8.4 "Data Cache Control" on page 22 for more on how to use PREF. If the effective address computed by the PREF instruction does not translate in the TLB (i.e. the address would cause a TLBL exception), no exception is generated and the cache is unchanged. The Au1 core implements the following PREF instruction hints: * 0x00 - Normal load * 0x04 - Streaming load A PREF instruction using any other hint value becomes a NOP for the Au1 core.
2.6.3
WAIT Instruction
The WAIT instruction places the Au1 core in one of two low power modes: IDLE0 and IDLE1. The low power mode is encoded in the WAIT instruction bits 24:6 (implementation-dependent code). A value of 0 selects IDLE0, and the value 1 selects IDLE1. Other values are not supported and must not be used. In the IDLE0 low power mode, the Au1 core stops clocks to all possible core units but continues to snoop the SBUS to maintain data coherency. In the IDLE1 low power mode, the Au1 core stops clocks to all possible core units, including the data cache, so data coherency is no longer maintained. In either Idle mode, the general purpose registers and the CP0 registers are preserved, so that when Idle mode is exited by an appropriate event, the Au1 core resumes processing instructions in exactly the same context as prior to entering Idle mode. To enter the low power mode, the WAIT instruction must be followed by at least four NOPs, and the entire instruction sequence must be fetched from the instruction cache. More specifically, if the core fetches the WAIT and NOP instructions from main memory, then the mechanisms for accessing memory will prevent the core from entering low power mode. This is the recommended code sequence: .global au1_wait au1_wait: la t0,au1_wait # obtain address of au1_wait cache 0x14,0(t0) # fill icache with first 8 insns cache 0x14,32(t0) # fill icache with next 8 insns sync nop wait 0 nop nop nop nop j ra When the Au1 core is in Idle mode, the Count register increments at an unpredictable rate; therefore the Count/Compare registers can not be used as the system timer tick when using the WAIT instruction to enter an Idle mode.
AMD AlchemyTM AU1500TM Processor Data Book
29
www..com
30361D CPU
2.7
Coprocessor 0
Coprocessor 0 (CP0) is responsible for virtual memory, cache and system control. The MIPS32 ISA provides for differentiation of the CP0 implementation. The Au1 core has a unique CP0 that is compliant with MIPS32 specification. The Au1 CP0 registers are listed in Table 2-7.
Table 2-7. Coprocessor 0 Register Definitions
Register Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 17 18 18 19 19 20 21 22 23 24 25 25 26 27 28 28 29 29 30 31 Note 1. Sel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 DTag DData ITag IData ErrorEPC DESave Scratch Debug DEPC Reserved Reserved BadVAddr Count EntryHi Compare Status Cause EPC PRId Config Config1 LLAddr WatchLo IWatchLo WatchHi IWatchHi Register Name Index Random EntryLo0 EntryLo1 Context PageMask Wired Description Pointer into TLB array Pseudo-random TLB pointer Low half of TLB entry for even pages Low half of TLB entry of odd pages Pointer to a page table entry Variable page size select Number of locked TLB entries Reserved Bad virtual address CPU cycle count High half of TLB entries CPU cycle count interrupt comparator Status Reason for last exception Program Counter of last exception Processor ID and Revision Configuration Registers (aka Config0) Configuration Register 1 Load Link Address Data memory break point low bits Instruction fetch breakpoint low bits Data memory break point high bits Instruction fetch breakpoint high bits Reserved Reserved Scratch register EJTAG control register PC of EJTAG debug exception Reserved Reserved Reserved Reserved Data cache tag value Data cache data value Instruction cache tag value Instruction cache data value Program counter at last error EJTAG debug exception save register Compliance (Note 1) Required Required Required Required Required Required Required Reserved Required Required Required Required Required Required Required Required Required Required Optional Optional Optional Optional Optional Reserved Reserved Au1 Optional Optional Au1 Reserved Au1 Reserved Reserved Reserved Au1 Au1 Au1 Au1 Required Optional
A compliance of "Required" denotes a register required by the MIPS32 architecture. "Optional" denotes an optional register in the MIPS32 architecture which is implemented in the Au1 core. "Au1" denotes an optional register unique to the Au1 core. "Reserved" denotes a register that is not implemented.
30
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.1
Index Register (CP0 Register 0, Select 0)
The Index register is required for TLB-based virtual address translation units.
Index Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P 0 Def. X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 Register 0, Select 0 543210 Index 00XXXXX
9 0
8 0
7 0
6
Bits 31 30:5 4:0
Name P Reserved Index
Description Probe Failure. Must always write zeros, always reads zeros TLB Index
R/W R R R/W
Default UNPRED 0 UNPRED
2.7.2
Random Register (CP0 Register 1, Select 0)
The Random register is required for TLB-based virtual address translation units.
Random Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 Register 1, Select 0 543210 Random 0011111 6
9 0
8 0
7 0
Bits 31:5 4:0
Name Reserved Random
Description Must always write zeros, always reads zeros TLB Random Index
R/W R R
Default 0 31
2.7.3
EntryLo0, EntryLo1 Register (CP0 Registers 2 and 3, Select 0)
The EntryLo0 and EntryLo1 registers are required for TLB-based virtual address translation units.
EntryLo0, EntryLo1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 PFN Def. 0 0 X X X X X X X X X X X X X X X X X X X X X CP0 Registers 2 and 3, Select 0 76543210 C DVG XXXXXXXXX 8
Bits 31:30 29:6 5:3 2 1 0
Name Reserved PFN C D V G
Description Ignored on writes, returns zero on read Page Frame Number. Corresponds to physical address bits 35..12. Cache coherency attribute of the page. See Table 2-3 "Cache Coherency Attributes (CCA)" on page 19. Dirty bit. Valid bit Global bit
R/W R R/W R/W R/W R/W R/W
Default 0 UNPRED UNPRED UNPRED UNPRED UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
31
www..com
30361D CPU
2.7.4
Context Register (CP0 Register 4, Select 0)
The Context register is required for TLB-based virtual address translation units.
Context Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PTEBase BadVPN2 Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 4, Select 0 543210 0 XXX0000 6
8 X
7 X
Bits 31:23 22:4 3:0
Name PTEBase BadVPN2 Reserved
Description Used by the operating system as a pointer into the current PTA array in memory. Contains virtual address bits 31..13 upon a TLB exception. Reserved
R/W R/W R R
Default UNPRED UNPRED 0
2.7.5
PageMask Register (CP0 Register 5, Select 0)
The PageMask register is required for TLB-based virtual address translation units.
PageMask Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 Mask Def. 0 0 0 X X X X X X X X X X X X X X X X 0 0 0 CP0 Register 5, Select 0 543210 0 0 0 0 0 0
9 0
8 0
7 0
6 0 0
Bits 31:29 28:13
Name Reserved Mask
Description Ignored on write, returns zero on read. The Mask field is a bit mask in which a "1" bit indicates that the corresponding bit of the virtual address should not participate in the TLB match. See Table 2-4 "Values for Page Size and PageMask Register" on page 26. Ignored on write, returns zero on read.
R/W R R/W
Default 0 UNPRED
12:0
Reserved
R
0
2.7.6
Wired Register (CP0 Register 6, Select 0)
The Wired register is required for TLB-based virtual address translation units.
Wired Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 Register 6, Select 0 543210 Wired 0000000
9 0
8 0
7 0
6
Bits 31:5 4:0
Name Reserved Wired
Description Ignored on write, returns zero on read. TLB wired boundary
R/W R R/W
Default 0 0
32
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.7
BadVAddr Register (CP0 Register 8, Select 0)
The BadVAddr register is required for TLB-based virtual address translation units.
BadVAddr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BadVAddr Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 8, Select 0 543210 X X X X X X
8 X
7 X
6 X
Bits 31:0
Name BadVAddr
Description Bad virtual address
R/W R
Default UNPRED
2.7.8
Count Register (CP0 Register 9, Select 0)
The Count register is a required register for a constant rate timer. This counter increments 1:1 with the core frequency.
Count Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Count Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 Register 9, Select 0 543210 0 0 0 0 0 0
9 0
8 0
7 0
6 0
During IDLE0 or IDLE1 mode, the Count register increments at an unpredictable rate; therefore the Count/Compare registers can not be used as the system timer tick when using the WAIT instruction to enter an Idle mode. During Sleep mode, this register will not increment.
Bits 31:0
Name Count
Description Interval counter
R/W R/W
Default 0
2.7.9
EntryHi Register (CP0 Register 10, Select 0)
The Index register is required for TLB-based virtual address translation units.
EntryHi Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VPN2 0 Def. X X X X X X X X X X X X X X X X X X X 0 0 0 CP0 Register 10, Select 0 6543210 ASID XXXXXXX
9 0
8 0
7 X
Bits 31:13 12:8 7:0
Name VPN2 Reserved ASID
Description Virtual address bits 31..13. Ignored on write, returns zero on read. Address space identifier
R/W R/W R R/W
Default UNPRED 0 UNPRED
2.7.10
Compare Register (CP0 Register 11, Select 0)
The Compare register is a required register for generating an interrupt from the constant rate timer.
Compare Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Compare Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 11, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name Compare
Description Interval counter compare value
R/W R/W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
33
www..com
30361D CPU
2.7.11
Status Register (CP0 Register 12, Select 0)
The Status register is a required register for general control of the processor.
Status Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0 0 0 CU0 RP 0 RE 0 0 BEV 0 SR NMI 0 0 0 IM
9 0
8 0
7
0
Def. 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
CP0 Register 12, Select 0 6543210 0 0 UM 0 ERL EXL IE 0000100
Bits 31 30 29 28 27 25 22 20 19 15:8 4 3 2 1 0
Name CU3 CU2 CU1 CU0 RP RE BEV SR NMI IM UM R0 ERL EXL IE
Description This bit is zero. Coprocessor 3 is not implemented. This bit is zero. Coprocessor 2 is not implemented. This bit is zero. Coprocessor 1 is not implemented. Controls access to coprocessor 0. Reduced power. This bit has no effect. Reverse-endian. Boot exception vectors. Soft reset. Non-maskable interrupt Interrupt mask User-mode. This bit is zero; Supervisor-mode not implemented Error Level Exception Level Interrupt Enable
R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Default 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
2.7.12
Cause Register (CP0 Register 13, Select 0)
The Cause register is a required register for general exception processing.
Cause Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IV WP 0 IP BD 0 CE 0 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 CP0 Register 13, Select 0 6543210 ExcCode 0 0000000
9 0
8 0
7 0 0
Bits 31 29:28 23 22 15:10 9:8 6:2
Name BD CE IV WP IP[7:2] IP[1:0] ExcCode
Description Exception in branch delay slot Coprocessor error Interrupt vector Watchpoint exception deferred Hardware interrupts pending Software interrupts pending Exception Code
R/W R R R/W R/W R R/W R
Default 0 0 0 0 0x20 0 0
34
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.13
Exception Program Counter (CP0 Register 14, Select 0)
The Exception Program Counter (EPC) register is a required register for general exception processing.
EPC Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 EPC Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 14, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name EPC
Description Exception Program Counter
R/W R/W
Default UNPRED
2.7.14
Processor Identification (CP0 Register 15, Select 0)
The PRId register is a required register for processor identification.
PRId Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Company Options Company ID Processor ID Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 CP0 Register 15, Select 0 6543210 Revision 0000000
9 1
8 0
7 0
Bits 31:24
Name Company Options
Description System-on-a-chip (SOC) identification: 0 1 2 Au1000 AU1500 Au1100
R/W R
Default 1
23:16 15:8
Company ID Processor Core ID
Company ID assigned by MIPS Technologies. AMD's ID = 3. Identifies the core revision: 0 1 2 Reserved Au1 revision 1 Au1 revision 2
R R
3 2
7:0
Revision
Contains a manufacturing-specific revision level. 0 1 2 Silicon stepping AB; silicon revision 1.0 Silicon stepping AC; silicon revision 1.1 Silicon stepping AD; silicon revision 1.2
R
SOC specific
AMD AlchemyTM AU1500TM Processor Data Book
35
www..com
30361D CPU
2.7.15
Configuration Register 0 (CP0 Register 16, Select 0)
The Config0 register is a required register for various processor configuration and capability.
Config0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 M CT DD CD UM WD NM SM OD 0 0 TM BE AT AR Def. 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 CP0 Register 16, Select 0 6543210 0 K0 0000011
87 MT 001
9
Bits 31 30:26 25 24 23 22 21 20 19 16 15 14:13 12:10 9:7 2:0
Name M CT DD CD UM WD NM SM OD TM BE AT AR MT K0
Description Denotes Config1 register available at select 1 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Reserved, must write 0 Indicates the endian mode. Architecture type is MIPS32. Architecture revision is Revision 1. MMU type is standard TLB. KSEG0 is cacheable, coherent.
R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W
Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 3
2.7.16
Configuration Register 1 (CP0 Register 16, Select 1)
The Config1 register is a required register for various processor configuration and capability.
Config1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IS IL IA DS DL 0 MMU Size - 1 Def. 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 CP0 Register 16, Select 1 876543210 DA C2 MD PC WR CA EP FP 0110001010 9
Bits 30:25 24:22 21:19 18:16 15:13 12:10 9:7 6 5 4 3 2 1 0
Name MMU Size - 1 IS IL IA DS DL DA C2 MD PC WR CA EP FP
Description Number of entries in the TLB minus one. The TLB has 32 entries. Instruction cache sets per way is 128. Instruction cache line size is 32 bytes. Instruction cache associativity is 4-way. Data cache sets per way is 128. Data cache line size is 32 bytes. Data cache associativity is 4-way. Coprocessor 2 is not implemented. Always returns zero on read. Performance Counter registers are not implemented. Watchpoint registers are implemented. Code compression is not implemented. EJTAG is implemented. FPU is not implemented.
R/W R R R R R R R R R R R R R R
Default 31 1 4 3 1 4 3 0 0 0 1 0 1 0
36
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.17
Load Linked Address Register (CP0 Register 17, Select 0)
The LLAddr register provides the physical address of the most recent Load Linked instruction.
LLAddr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LLAddr Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 17, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name LLAddr
Description Load Linked Address
R/W R
Default UNPRED
2.7.18
Data WatchLo Register (CP0 Register 18, Select 0)
The WatchLo and WatchHi registers are the interface to the data watchpoint facility.
WatchLo Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VAddr Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 18, Select 0 6543210 0RW XXXX000
8 X
7 X
Bits 31:3 1 0
Name VAddr R W
Description The virtual address to match If this bit is a one, then watch exceptions are enabled for loads that match the address. If this bit is a one, then watch exceptions are enabled for stores that match the address.
R/W R/W R/W R/W
Default UNPRED 0 0
2.7.19
Instruction WatchLo Register (CP0 Register 18, Select 1)
The IWatchLo and IWatchHi registers are the interface to the instruction watchpoint facility.
IWatchLo Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VAddr Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 18, Select 1 6543210 I00 XXXX000
8 X
7 X
Bits 31:3 2
Name VAddr I
Description The virtual address to match If this bit is a one, then watch exceptions are enabled for instruction accesses that match the address.
R/W R/W R/W
Default UNPRED 0
AMD AlchemyTM AU1500TM Processor Data Book
37
www..com
30361D CPU
2.7.20
Data WatchHi Register (CP0 Register 19, Select 0)
The WatchLo and WatchHi registerS are the interface to the data watchpoint facility.
WatchHi Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 MG 0 ASID 0 Def. 1 X 0 0 0 0 0 0 X X X X X X X X 0 0 0 0 X X X CP0 Register 19, Select 0 76543210 Mask 0 XXXXXX000 8
Bits 31 30 23:16 11:3
Name M G ASID Mask
Description Another pair of Watch registers is implemented at the next Select index. If this bit is one, then the ASID field is ignored and any address that matches causes a watch exception. ASID value which is required to match that in the EntryHi register if the G bit is zero in the WatchHi register. Any bit in this field that is a one inhibits the corresponding address bit from participating in the address match.
R/W R R R/W R/W
Default 1 UNPRED UNPRED UNPRED
2.7.21
Instruction WatchHi Register (CP0 Register 19, Select 1)
The IWatchLo and IWatchHi registers are the interface to the instruction watchpoint facility.
IWatchHi Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ASID 0 0G 0 Def. 0 X 0 0 0 0 0 0 X X X X X X X X 0 0 0 0 X X X CP0 Register 19, Select 1 76543210 Mask 0 XXXXXX000 8
Bits 30 23:16 11:3
Name G ASID Mask
Description If this bit is one, then the ASID field is ignored and any address that matches causes a watch exception. ASID value which is required to match that in the EntryHi register if the G bit is zero in the WatchHi register. Any bit in this field that is a one inhibits the corresponding address bit from participating in the address match.
R/W R R/W R/W
Default UNPRED UNPRED UNPRED
2.7.22
Scratch Register (CP0 Register 22, Select 0)
The Scratch register exists for the convenience of software. Upon a read, this register returns the value last written into it.
Scratch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Scratch Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 22, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name Scratch
Description This register is present for the convenience of software.
R/W R/W
Default UNPRED
38
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.23
Debug Register (CP0 Register 23, Select 0)
The Debug register is part of the interface to the EJTAG facility.
Debug Bit 31
DBD
30
DM
29
0
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LSNM 0 001 DExcCode
9
0
8
SSt
7
0
6
0
CP0 Register 23, Select 0 543210
DINT 0 DBp DSS
Def. 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
Bits 31 30 28 17:15 14:10 8 5 1 0
Name DBD DM LSNM 001 DExcCode SSt DINT DBp DSS
Description Debug exception in branch delay slot. If this bit is a one, then in debug mode. Load/stores are performed in the normal fashion when in debug mode. EJTAG version 2.5 Cause[ExcCode] for normal exceptions in debug mode. Enable single step mode Last debug exception was asynchronous debug interrupt Last debug exception was an SDBPP instruction Last debug exception was a single step
R/W R R R/W R R R/W R R R
Default UNPRED 0 0 001 UNPRED 0 0 0 0
2.7.24
DEPC Register (CP0 Register 24, Select 0)
The DEPC register is part of the interface to the EJTAG facility.
DEPC Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DEPC Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 24, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name DEPC
Description Debug exception program counter.
R/W R/W
Default UNPRED
2.7.25
Note:
Data Cache Tag Register (CP0 Register 28, Select 0)
This register corresponds to the TagLo register in the MIPS32 ISA specification.
The DTag and DData registers are the interface to the data cache array. This cache interface is unique to the Au1.
DTag CP0 Register 28, Select 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00DSLV TAG MRU NMRU LRU Def. X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X
Bits 31:12 11:10 9:8 7:6 3 2 1 0
Name TAG MRU NMRU LRU D S L V
Description TAG represents bits [31:12] of a physical memory address. Bits [35:32] of the physical address are always zero. Most recently used way. Next most recently used way. Least recently used way. Cache line is dirty (modified). Cache line is shared (for data cache snoops). Locked. This bit is set by the user to prevent overwriting of the cache line. Cache line valid.
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default UNPRED UNPRED UNPRED UNPRED UNPRED UNPRED UNPRED UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
39
www..com
30361D CPU
2.7.26
Note:
Data Cache Data Register (CP0 Register 28, Select 1)
This register corresponds to the DataLo register in the MIPS32 ISA specification.
CP0 Register 28, Select 1 6543210 X X X X X X X
The DTag and DData registers are the interface to the data cache array.
DData Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Data Def. X X X X X X X X X X X X X X X X X X X X X X X
8 X
7 X
Bits 31:0
Name Data
Description Data from the data cache line.
R/W R
Default UNPRED
2.7.27
Note:
Instruction Cache Tag Register (CP0 Register 29, Select 0)
This register corresponds to the TagHi register in the MIPS32 ISA specification.
The ITag and IData registers are the interface to the instruction cache array. This cache interface is unique to the Au1.
ITag CP0 Register 29, Select 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAG MRU NMRU LRU 0 LV Def. X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 X X
Bits 31:12 11:10 9:8 7:6 1 0
Name TAG MRU NMRU LRU L V
Description TAG represents bits [31:12] of a physical memory address. Bits [35:32] of the physical address are always zero. Most recently used way. Next most recently used way. Least recently used way. Locked. This bit is set by the user to prevent overwriting of the cache line. Cache line valid.
R/W R/W R/W R/W R/W R/W R/W
Default UNPRED UNPRED UNPRED UNPRED UNPRED UNPRED
2.7.28
Note:
Instruction Cache Data Register (CP0 Register 29, Select 1)
This register corresponds to the DataHi register in the MIPS32 ISA specification.
CP0 Register 29, Select 1 6543210 X X X X X X X
The ITag and IData registers are the interface to the instruction cache array.
IData Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Data Def. X X X X X X X X X X X X X X X X X X X X X X X
8 X
7 X
Bits 31:0
Name Data
Description Data from the instruction cache line.
R/W R
Default UNPRED
40
AMD AlchemyTM AU1500TM Processor Data Book
www..com
CPU 30361D
2.7.29
ErrorEPC Register (CP0 Register 30, Select 0)
The ErrorEPC register is a required register for exception processing.
ErrorEPC Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ErrorEPC Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 30, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name ErrorEPC
Description Error Exception Program Counter
R/W R/W
Default UNPRED
2.7.30
DESAVE Register (CP0 Register 31, Select 0)
The DESAVE register is part of the interface to the EJTAG facility.
DESAVE Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DESAVE Def. X X X X X X X X X X X X X X X X X X X X X X X CP0 Register 31, Select 0 6543210 X X X X X X X
8 X
7 X
Bits 31:0
Name DESAVE
Description Debug save scratch register, for debug handlers.
R/W R/W
Default UNPRED
2.8
System Bus (SBUS)
The Au1 core communicates with memories and peripherals via the System Bus (SBUS). The SBUS is a 36-bit physical address and 32-bit data bus which is internal to the AU1500 processor. The SBUS is the coherency point within the AU1500 processor.
2.8.1
SBUS Arbitration
The SBUS supports multiple masters--the Au1 core and peripheral DMA engines. The SBUS is granted to the masters in a least-recently-used/fair scheme. This scheme prevents two or more masters from consuming the entire SBUS bandwidth, while permitting low latency access to the SBUS for masters which request the bus infrequently (such as peripherals). The SBUS requestors in the AU1500 processor are: * Au1 core * Ethernet MAC controller (2) * USB Host controller * PCI controller * DMA controller The Au1 presents a single request to the SBUS arbiter for the three possible requestors: the data cache, the instruction cache and the write buffer. The data cache has the highest priority and the write buffer the lowest priority among the three requests. However, the write buffer priority becomes the highest when the data cache requests a load to an address in the write buffer to allow the write buffer to empty prior to fulfilling the data cache load. The SBUS arbiter has four bus arbitration slots for handling the SBUS masters: * Slot 0: Au1 core (data cache, instruction cache, write buffer) * Slot 1: Ethernet MAC controllers * Slot 2: DMA controller * Slot 3: USB host controller and PCI controller
AMD AlchemyTM AU1500TM Processor Data Book
41
www..com
30361D CPU
The arbitration scheme for the SBUS is round-robin; that is, each bus master slot has an equal opportunity to obtain access to the SBUS. For a particular SBUS master X, if no other SBUS masters request the bus, then bus master X immediately wins the SBUS. By contrast, if all other SBUS masters request the bus, then bus master X must wait for three other SBUS master slots to transfer before it wins the SBUS, as shown in Figure 2-4.
Req A Req B Req C Req X SBUS A B C X
Figure 2-4. SBUS Arbitration
When a SBUS master wins arbitration of the SBUS, it performs transfers to/from the integrated peripherals, SDRAM, or the Static bus.
2.8.2
SBUS Coherency Model
The SBUS is the coherency point within the AU1500 processor. An SBUS master (i.e. Au1 core or peripheral DMA engine) marks each SBUS transaction as either coherent or non-coherent. SBUS transactions marked as coherent are then snooped by all caching masters (i.e. Au1 data cache). An SBUS transaction that is marked non-coherent is not snooped by caching masters. The Au1 core is a coherent, caching master. The Au1 data cache snoops SBUS transactions; if a read transaction hits in the data cache then the data cache provides the data, if a write transaction hits in the data cache then the data cache array is updated with the new data. The integrated peripherals (with DMA engines) can be configured for coherent or non-coherent operation. The `C' bit in the peripheral/module enable register directs whether peripheral SBUS transactions are to be marked coherent or non-coherent. If a peripheral is configured for coherent operation, then it is not necessary to writeback and invalidate Au1 data cache lines which hit in the memory buffers used by DMA engines. If, on the other hand, the peripheral is configured for noncoherent operation, then software must ensure that memory buffers used by the DMA engines are not in the data cache (else the data cache and/or the memory buffer may contain old, stale data). The decision to use, or not use, coherent SBUS transactions is left to the application. However, peripheral device drivers using coherent SBUS transactions will perform better than drivers not using coherent SBUS transactions since the need to writeback the data cache is eliminated.
2.9
EJTAG
EJTAG is supported per the MIPS EJTAG Rev. 2.5 specification. EJTAG provides for CPU and board level bring-up and debug.
42
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Memory Controllers 30361D
3.0Memory Controllers
The AU1500 processor contains two memory controllers, one for SDRAM and one for static devices. The SDRAM controller supports SDRAM, SMROM and SyncFlash. The static device controller supports SRAM, Flash, ROM, page mode ROM, PCMCIA/Compact Flash devices, and an external LCD controller interface. Both memory controllers support software configurable memory address spaces. This allows designers to keep memory regions contiguous. For example, a system with 4 MB initially installed would locate the memory at physical address 0. Normally, adding 16 MB would create a 12 MB gap in the memory map. With the address configuration options in the AU1500 the 4 MB can be relocated to start at 16 MB, and the new memory can be located at 0 to allow a 20 MB contiguous memory pool. All registers in the Memory Controller block are located off of the base address shown in Table 3-1.
3
Table 3-1. Memory Controller Block Base Address
Name mem Physical Base Address 0x0 1400 0000 KSEG1 Base Address 0xB400 0000
The system designer has the choice of booting from 32-bit Flash, 16-bit Flash, 32-bit SMROM, and 32-bit SyncFlash. The ROMSEL and ROMSIZE configuration is discussed in more detail in Section 9.3 "Boot" on page 182. Table 9-1 on page 182 shows how the state of ROMSEL and ROMSIZE determines where the processor boots from.
AMD AlchemyTM AU1500TM Processor Data Book
43
www..com
30361D SDRAM Memory Controller
3.1
SDRAM Memory Controller
The SDRAM memory controller of the AU1500 processor is designed for glueless interface to one, two, or three ranks of SDRAM or SMROM. SDRAM and SyncFlash are run at 1/2 the internal System Bus (SBUS) speed. The SBUS defaults to 1/2 the processor clock speed so that SDRAM or SyncFlash will run at 99 MHz with a 396 MHz AU1500. SMROM operates at 1/4 the speed of the SBUS. The SBUS divider is programmable, see Section 8.4.4 "Device Power Management - Sleep" on page 174 for more information. The SDRAM interface supports three chip selects (SDCS[2:0]#), corresponding to three ranks of SDRAM. Each chip select can be configured to support either SDRAM or SMROM. In addition, chip select 0 can be configured for SyncFlash (no other chip selects can be used to support SyncFlash). For chip selects configured as SDRAM or SyncFlash (on chip select 0) the controller keeps one row open for up to four banks per chip select allowing fast accesses and reducing the need to issue precharge cycles. Note: The SDRAM memory controller supports a maximum of two loads per chip select. When RESETIN# is negated, code is fetched from SMROM/SyncFlash if SMROM/SyncFlash boot is selected. When using SMROM or SyncFlash for boot, the SMROMCKE signal should be used for the SMROM/SyncFlash CKE. If SMROM or SyncFlash are being used (but not for boot), SDCKE should be used for the clock enable. After boot internal configuration registers can be written to enable SDRAM chip selects. When a chip select is enabled the SDCKE is driven asserted and clocks are started. Software must wait 10 s for the SDRAM clock to stabilize before any device specific initialization steps. All SDRAM/SMROM ranks must be 32 bits wide. Support is included for SDRAM with 2 or 4 banks, 11 to 13 row address bits, and 7 to 11 column address bits. It is also possible to send explicit commands to the SDRAM, under software control, for diagnostic, initialization, or power management purposes. SDRAM clocks keep running during a runtime reset to allow any transaction in progress to complete. This avoids the possibility of bus contention when the part is brought out of reset. Note that the SDRAM controller assumes the following external SDRAM configuration: * Burst Length = 8 * Addressing Mode = Sequential * Write Mode = Burst Read and Write
44
AMD AlchemyTM AU1500TM Processor Data Book
www..com
SDRAM Memory Controller 30361D
3.1.1
SDRAM Controller Programming Model
The SDRAM controller contains a number of registers which configure the operation of the interface. All registers in the SDRAM controller block are located off of the base address shown in Table 3-1 "Memory Controller Block Base Address" on page 43. Table 3-2 shows the memory map of the register block.
Table 3-2. SDRAM Configuration Registers
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 Register Name mem_sdmode0 mem_sdmode1 mem_sdmode2 mem_sdaddr0 mem_sdaddr1 mem_sdaddr2 mem_sdrefcfg mem_sdprecmd mem_sdautoref mem_sdwrmd0 mem_sdwrmd1 mem_sdwrmd2 mem_sdsleep mem_sdsmcke Force SDRAM into self refresh mode Toggle SMROMCKE pin Refresh Configuration and Timing Issue PRECHARGE to all enabled SDRAM chip selects Issue AUTO REFRESH to all enabled SDRAM chip selects Write data to SDCSn# SDRAM mode configuration register SDCSn# address configuration and enable Description SDRAM chip select n (SDCSn#) mode configuration register (timing and functionality)
Note 1. See Table 3-1 on page 43 for base address.
3.1.2
SDRAM Registers
Each chip select is configured by two registers, a mode register and an address configuration register. 3.1.2.1 Chip Select Mode Configuration Registers The format and reset values of the chip select mode configuration registers is shown in the following figure. The timing parameters (Tcl, Tcrd, Trp, Twr, Tmrd, and Tras) correspond directly to times shown in the SDRAM timing diagrams. Times are measured in SDRAM/SMROM clock cycles. The default values for chip select zero correspond to values for SMROM operation. Chip select 1 and 2 are configured with the slowest timing values at reset. Reserved fields should be written as zeros and ignored on read to preserve compatibility with future versions of the product.
mem_sdmode0 - CS0 Mode Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SF F SR BS RS CS Tras Tmrd Def. 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 1 mem_sdmode1 - CS1 Mode Configuration mem_sdmode2 - CS2 Mode Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 F SR BS RS CS Tras Tmrd Def. 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 1 Offset = 0x0000 43210 Trcd Tcl 01100 Offset = 0x0004 Offset = 0x0008 43210 Trcd Tcl 11111
87 Twr 11
65 Trp 11
87 Twr 11
65 Trp 11
AMD AlchemyTM AU1500TM Processor Data Book
45
www..com
30361D SDRAM Memory Controller
Bits 31:24 23
Name -- SF
Description Reserved, should be cleared. Selects SyncFlash operation. SyncFlash is available only on SDCS0#. For other chip selects, this bit is reserved and should be cleared. 0 1 SyncFlash is not being used. SyncFlash is being used.
R/W R R/W
Default 0 0
22
F
Setting the F bit allows the SDRAM controller to assume that no caching master except the core will access this memory space. This allows accesses to begin sooner. Note that the CPU core is the only possible caching master, so it is safe for the system designer to set this bit.
R/W
0
21
SR
Chip select operating mode. 0 1 SDRAM/SyncFlash operation. SMROM operation.
R/W
See above
20
BS
Select Number of Banks. 0 1 Chip select controls 2-bank SDRAM. Chip select controls 4-bank SDRAM.
R/W
See above
Note: This bit must be cleared for SMROM support. 19:18 RS This field sets the number of bits in the row address as shown below: RS Row Address Size 00 01 10 11 17:15 CS 11 12 13 Reserved R/W See above R/W See above
This field sets the number of bits in the column address as shown below: CS Column Size 000 7 001 8 010 9 011 10 100 11 All other values are reserved.
14:11
Tras
This field designates the minimum delay from a activate to a precharge command. (Tras + 1) is the actual number of clock cycles. This field sets the required delay from an external load of the SDRAM mode register (not the chip select mode register) to an activate command. (Tmrd + 1) is the actual number of clock cycles. The Twr field sets the write recovery time. This is the last data for a write to a precharge. This field is sometimes referred to a Tdpl. (Twr + 1) is the actual number of clock cycles. This field sets the time from precharge to the next activate command. (Trp + 1) is the actual number of clock cycles. This field sets the RAS to CAS delay. (Trcd + 1) is the actual number of clock cycles. This field sets the minimum CAS latency timing. This is the time from CAS to DATA on reads. (Tcl + 1) is the actual number of clock cycles.
R/W
15
10:9
Tmrd
R/W
3
8:7
Twr
R/W
3
6:5 4:3 2:0
Trp Trcd Tcl
R/W R/W R/W
3 See Above See Above
46
AMD AlchemyTM AU1500TM Processor Data Book
www..com
SDRAM Memory Controller 30361D
3.1.2.2 SDRAM Chip Select Address Configuration Registers (mem_sdaddrn) The SDRAM chip-select address configuration registers (mem_sdaddrn) assign an address range for each chip select. As shown below, each register contains a base address, an address comparison mask, and an enable bit.
mem_sdaddr0 - SDCS0# Address Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 E CSBA Def. 0 0 0 0 0 0 0 0 0 0 0 Rs 0 0 0 1 1 1 1 1 1 1 mem_sdaddr1 - SDCS1# Address Configuration mem_sdaddr2 - SDCS2# Address Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 E CSBA Def. 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Offset = 0x000C 543210 CSMASK 1111111 6 Offset = 0x0010 Offset = 0x0014 543210 CSMASK 1111111 6
9 1
8 1
7 1
9 1
8 1
7 1
Bits 31:21 20
Name -- E
Description Reserved, should be cleared. Enable. 0 1 Chip select is disabled. Chip select is enabled.
R/W R R/W
Default 0 0, except for mem_sdaddr0 (Note 1) 0x3FF, except for mem_sdaddr0 where the default value is 0x7F. 0x3FF
19:10
CSBA
Chip select base address. Specifies bits 31:22 of the physical base address for this chip select. (The lower bits of the base address are zero.) Chip select address mask. Specifies which bits of CSBA are used to decode this chip select.
R/W
9:0
CSMASK
R/W
Note 1. The E bits for the chip selects SDCS1# and SDCS2# are automatically cleared (disabled) coming out of a runtime or hardware reset. For SDCS0#, however, the reset value of the E bit depends on ROMSEL and ROMSIZE: SDCS0#'s E bit is set when the ROMSEL and ROMSIZE pins indicate that the SMROM/SyncFlash should be used for the boot vector (ROMSEL==1, ROMSIZE==0). See also Section 9.3 "Boot" on page 182.
Once enabled (E bit set), a chip select is asserted when the following condition is met: (phys_addr & addr_mask) == base_addr where phys_addr: addr_mask: base_addr: 32-bit physical address output on the internal SBUS (from the TLB for memory-mapped regions) (Bits 35:32 of the physical address are zeros.) address comparison mask taken from CSMASK chip select base address taken from CSBA
Note that chip select regions must be programmed so that each chip select occupies a unique area of the physical address space. Programming overlapping chip select regions results in undefined operation.
AMD AlchemyTM AU1500TM Processor Data Book
47
www..com
30361D SDRAM Memory Controller
3.1.2.3 Refresh Configuration Register The refresh configuration register sets the timing of SDRAM refresh for all chip selects. Since the timing for these signals apply to all chip selects, if different types of SDRAM is used the worst case timing must be applied. The format of the refresh configuration register is as follows:
mem_sdrefcfg - Refresh Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Trc Trpr E RI Def. 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Offset = 0x0018 3210 1 1 1 1
9 1
8 1
7 1
6 1
5 1
4 1
Bits 31:28
Name Trc
Description The Trc field specifies the minimum time from the start of an auto refresh cycle to an activate command for all SDRAM chip selects. (Trc + 1) is the actual number of clock cycles. This field specifies the minimum time from a precharge to the start of a refresh cycle for all SDRAM chip selects. This is used because a precharge all command is automatically initiated before an auto refresh command. This value should be programmed with the worst case Trp from the sdr_csmoden registers. (Trpm + 1) is the actual number of clock cycles. When this bit is set, refresh is enabled for all chip selects configured as SDRAM. Refresh Interval - This field specifies the maximum refresh interval in SBUS clocks for all SDRAM ranks. The refresh interval is for each individual refresh so for a system with a row address size of 12 (4096 rows) and memory with a refresh time of 64 ms (all rows), the individual refresh interval will be 15.7 s (64 ms/4096). With a SBUS clock of 198 MHz, the RI value should be 0xC24 (15.7 s / (1/198 MHz).
R/W R/W
Default 0xf
27:26
`
R/W
3
25 24:0
E RI
R/W R/W
0 0x1FFFFFF
3.1.2.4 Precharge All Command Register Writing any value to the mem_sdprecmd register issues a precharge all command to all enabled SDRAM chip selects. This can be used for initialization sequences that require certain operations to be performed in a deterministic order. Reading from the mem_sdprecmd register is unpredictable.
mem_sdprecmd - Precharge All Command Reg Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PA Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x001C 3210 X X X X
8 X
7 X
6 X
5 X
4 X
Bits 31:0
Name PA
Description Writing any value to PA will cause a precharge command to be issued to all enabled SDRAM chip selects.
R/W W
Default UNPRED
48
AMD AlchemyTM AU1500TM Processor Data Book
www..com
SDRAM Memory Controller 30361D
3.1.2.5 Auto Refresh Command Register Writing to the mem_sdautoref register performs an auto refresh command on all enabled SDRAM chip selects. This can be used for initialization sequences that require specific operations to be performed in a deterministic order. To insure future compatibility the value written should always be zero. Reading from the mem_sdautoref register will return the current value of the refresh timer.
mem_sdautoref - Auto Refresh Command Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 AR Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0020 3210 X X X X
8 X
7 X
6 X
5 X
4 X
Bits 31:0
Name AR
Description Writing a value to AR causes an AUTO REFRESH command to be issued to all enabled SDRAM chip selects.
R/W R/W
Default UNPRED
3.1.2.6 External SDRAM Mode Register Access The mem_sdwrmd0, mem_sdwrmd1, and mem_sdwrmd2 command registers allow software to directly write to the mode registers in SDRAM connected to each chip select. This can be used in initialization sequences that require certain operations be performed in a deterministic order.
mem_sdwrmd0 - Write CS0 SDRAM Mode mem_sdwrmd1 - Write CS1 SDRAM Mode mem_sdwrmd2 - Write CS2 SDRAM Mode Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BA WM Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0024 Offset = 0x0028 Offset = 0x002C 3210 X X X X
8 X
7 X
6 X
5 X
4 X
Bits 31:30
Name BA[1:0]
Description Bank address. These bits are reflected on the SDBA[1:0] signals. They can be used to write to the extended mode register (for synchronous Flash and battery RAM, for example). These bits must be cleared otherwise. The value written to this register is written to the external SDRAM mode register for the corresponding chip select.
R/W W
Default UNPRED
29:0
WM
W
UNPRED
3.1.2.7 SDRAM Sleep/Self Refresh Command Register Writing any value to this register performs sends a self refresh command on all enabled SDRAM chip selects. This command can be used for the SDRAM power down sequence which requires specific commands to be performed in a deterministic order. After performing self refresh the SDRAM controller will hold SDCKE low and wait until a Sleep exit sequence or reset is performed. For this reason nothing should access the SDRAM after this command has been issued.
mem_sdsleep -SDRAM Sleep Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SL Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0030 3210 X X X X
8 X
7 X
6 X
5 X
4 X
Bits 31:0
Name SL
Description Writing any value to SL will issue a self refresh command on all enabled chip selects.
R/W W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
49
www..com
30361D SDRAM Memory Controller
3.1.2.8 SMROMCKE Toggle Register Writing to this register causes the state of the SMROMCKE signal to change. SMROMCKE will default to high when booting from SMROM or Sync Flash. This is used during power-up configuration to change the SMROM burst size from 4 to 8 beats. This command register does not affect the SDRAM SDCKE signal.
mem_sdsmcke -SMROMCKE Toggle Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ST Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0034 3210 X X X X
8 X
7 X
6 X
5 X
4 X
Bits 31:0
Name ST
Description Writing to ST (regardless of the value written) inverts the current state of SMROMCKE.
R/W W
Default UNPRED
3.1.3
SDRAM Timing
The following figures show examples of typical read, typical write and refresh timing.
SDCLKn SDCKE SDCSn# SDRAS# SDCAS# SDWE# SDBA[1:0] SDA[12:0] SDQM#
Tcl
row (a/b) col (a) col (b) row (c) col (c) row (d)
Tmrd Tras Trcd Trp
SDD[31:0]
ACTIVATE READ
a1
READ ACTIVATE
b1
b2
READ
c1
c2
c3
c4
PRECHARGE
Mode Register Set
(1 beat)
(2 beat)
(4 beat)
activate
The above timing represents the following: 1. Tras = 4 (5 SDRAM clock cycles) 2. Trp = 0 (1 SDRAM clock cycles) 3. Trcd = 1 (2 SDRAM clock cycles) 4. Tcl = 1 (2 SDRAM clock cycles) 5. Tmrd = 0 (2 SDRAM clock cycles) The above timing is presented to concisely display the different SDRAM timing parameters. The functional bus behavior may differ from that displayed.
Figure 3-1. SDRAM Typical Read Timing
50
AMD AlchemyTM AU1500TM Processor Data Book
www..com
SDRAM Memory Controller 30361D
SDCLKn SDCKE SDCSn# SDRAS# SDCAS# SDWE# SDBA[1:0] SDA[12:0] SDQM#
Twr
row (a/b) col (a) col (b) row (c) col (c) row (d)
Tmrd Tras Trcd Trp
SDD[31:0]
ACTIVATE
a1
WRITE
b1
b2
c1
WRITE
c2
PRECHARGE ACTIVATE
WRITE ACTIVATE
(1 beat) Mode Register Set
(2 beat)
(2 beat)
The above timing represents the following: 1. Tras = 4 (5 SDRAM clock cycles) 2. Trp = 0 (1 SDRAM clock cycles) 3. Trcd = 1 (2 SDRAM clock cycles) 4. Tmrd = 0 (1 SDRAM clock cycles) The above timing is presented to concisely display the different SDRAM timing parameters. The functional bus behavior may differ from that displayed.
Figure 3-2. SDRAM Typical Write Timing
SDCLK[2:0] SDCKE Trpm SDCS[2:0]# CMD
PRECHARGE ALL AUTO REFRESH ACTIVATE
Trc
This example assumes that all SDCLK ranks ([2:0]) are enabled. The above timing represents the following: 1. Trpm = 3 (4 SDRAM clock cycles) 2. Trc = 3 (4 SDRAM clock cycles)
Figure 3-3. SDRAM Refresh Timing
AMD AlchemyTM AU1500TM Processor Data Book
51
www..com
30361D SDRAM Memory Controller
3.1.4
SDRAM Hardware Considerations
Table 3-3 shows the signals associated with the SDRAM interface.
Table 3-3. SDRAM Signals
Signal SDA[12:0] Input/ Output O Description Address Outputs. A0-A12 are driven during the ACTIVE command (row-address A0A12) and READ/WRITE command to select one location out of the memory array in the respective bank. The address outputs also provide the opcode during a LOAD MODE REGISTER command.
WRITE
SDBA[1:0]
O
Bank Address Outputs. SDBA1 and SDBA0 define to which bank the ACTIVE, READ, or PRECHARGE command is being applied. The SDBA signal values are programmed in mem_sdwrmdn[BA]. SDRAM data bus.
SDD[31:0] SDQM[3:0]#
IO O
Input/Output Mask. SDQM# is a mask signal for write accesses and an output enable signal for read accesses. SDQM0# masks SDD[7:0], SDQM1# masks SDD[15:8], SDQM2# masks SDD[23:16], SDQM3# masks SDD[31:24]. Command Outputs. SDRAS#, SDCAS# and SDWE# (along with SDCSn#) define the command being sent to the SDRAM rank.
SDRAS# SDCAS# SDWE# SDCLK[2:0]
O O O O
Clock output corresponding to each of the three chip selects. Clock speed is 1/2 SBUS frequency when corresponding SDCSn# is set to SDRAM or SyncFlash, 1/4 SBUS frequency when corresponding SDCSn# is set to SMROM. Programmable chip selects (3 ranks). Clock enable for SDRAM. Synchronous Mask ROM Clock Enable. This signal must be pulled high if the system is booting from SMROM. Muxed with GPIO[6]. If ROMSEL and ROMSIZE are configured to boot from Synchronous Mask ROM, SMROMCKE will control the pin out of reset, else GPIO[6] will control the pin out of reset.
SDCS[2:0]# SDCKE SMROMCKE
O O O
52
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
3.2
Static Bus Controller
The static bus controller provides a general purpose interface to a variety of external peripherals and memory devices. Each of the four static bus chip selects may be programmed to support standard Flash memory, ROM, Page Mode Flash/ ROM, SRAM, I/O peripherals, PCMCIA/Compact Flash devices, or an LCD controller. Because of the similarity of Compact Flash and PCMCIA, references to PCMCIA should be taken as applicable to Compact Flash except where noted. The AU1500 processor allows control of different device types by reconfiguring what control signals chip select n manages based on how the device type field (DTY) is encoded in the mem_stcfgn register. All device types use the same address and data bus signals, RAD[31:0] and RD[31:0]. Descriptions of all device types are provided in Section 3.2.2 "Static RAM, I/O Device and Flash Device Types" on page 60, Section 3.2.3 "PCMCIA/Compact Flash Device Type" on page 62, and Section 3.2.4 "LCD Controller Device Type" on page 68. A read to the static bus causes a 32-bit access. This can cause a potential problem with volatile devices because a single 16-bit read results in two 16-bit reads on the external bus. Chip selects may be programmed for fixed access times or an external wait signal may be used to provide a variable delay per access. While the static bus controller is a synchronous device internally, no external clock is available to reference the control signals. The internal clock comes from the SBUS clock. Configuring the SBUS clock determines the internal reference for the static controller and associated timings.
3.2.1
Static Controller Programming Model
The properties of each static controller chip select are determined by a set of registers. All registers in the Static Controller block are located off of the base address shown in Table 3-1 "Memory Controller Block Base Address" on page 43. Table 34 shows the registers and offsets for the static bus controller. After modifying the configuration of a chip select, software must issue a SYNC instruction before write accesses to the chip select are allowed.
Table 3-4. Static Bus Controller Configuration Registers
Offset (Note 1) 0x1000 0x1004 0x1008 0x1010 0x1014 0x1018 0x1020 0x1024 0x1028 0x1030 0x1034 0x1038 Register Name mem_stcfg0 mem_sttime0 mem_staddr0 mem_stcfg1 mem_sttime1 mem_staddr1 mem_stcfg2 mem_sttime2 mem_staddr2 mem_stcfg3 mem_sttime3 mem_staddr3 Description Configuration for RCS0# Timing parameters for RCS0# Address region control for RCS0# Configuration for RCS1# Timing parameters for RCS1# Address region control for RCS1# Configuration for RCS2# Timing parameters for RCS2# Address region control for RCS2# Configuration for RCS3# Timing parameters for RCS3# Address region control for RCS3#
Note 1. See Table 3-1 on page 43 for base address.
AMD AlchemyTM AU1500TM Processor Data Book
53
www..com
30361D Static Bus Controller
3.2.1.1 Static Bus Configuration Registers The static bus configuration registers (mem_stcfgn) configure the basic properties of each chip select. Support is included for static RAM, Flash, ROM, PCMCIA, LCD, and other types of I/O devices. When programming a chip select as an I/O, LCD, or PCMCIA device the address comparison mask will expect an address with the upper nibble set as shown in Table 3-5 "Device Type Encoding" on page 55 for the different device types. The TLB must be set up accordingly to map addresses to the memory region captured by the associated chip select. For example, to configure the TLB for use with an LCD controller, bits 29:26 of CoProcessor register Entry Lo must be 0b1110 (in addition to the other steps necessary to set up the TLB). These bits represent address bits 35:32 of the physical address which must be 0xE in order for the address to match successfully when a chip select is enabled as an LCD device. Since the RAM and Flash have an upper nibble of zero, it is not necessary to use the TLB to access devices set up with these types.
mem_stcfg0 Offset = 0x1000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BV D5 AV BE TS EW H BS PM RO DTY Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rs 0 0 0 0 1 1 mem_stcfg1 mem_stcfg2 mem_stcfg3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x1010 Offset = 0x1020 Offset = 0x1030 9876543210 BE TS EW H BS PM RO DTY 00000000000
Bits 31:13 12
Name -- BV
Description Reserved, should be cleared. Burst size visible. When this bit is set the burst size for static transfers will be output for chip selects not configured as LCD or PCMCIA. The burst size output is one less than the number of 32-bit words to be transferred. For 16-bit chip selects twice as many beats will occur. The mapping of the burst size to pins is shown in Table 3-6 "Burst Size Mapping" on page 55. This bit is a global attribute and is present only in mem_stcfg0. Divide by 5. Setting this bit will divide the SBUS clock by 5 to generate LCLK. When D5 is cleared the SBUS clock is divided by 4 to generate LCLK. This bit is a global attribute and is present only in mem_stcfg0. Address visible. Setting this bit will place the address for all internal accesses to the SBUS on the static address bus. This is intended to be used as a debug aid and should not be used during normal operation as it will increase system power usage. This bit is a global attribute and is present only in mem_stcfg0. Endianness. 0 1 Little Endian Big Endian
R/W R R/W
Default 0 0
11
D5
R/W
0
10
AV
R/W
0
9
BE
R/W
0
Program this bit to match the endianness of the processor. This bit should not be set for PCMCIA. 8 TS Time scale for chip select timing parameters. 0 Do not scale the timing parameters. 1 Multiply the timing parameters by a factor of four. This option allows for longer access times. 7 EW When the EW bit is set the EWAIT# input is allowed to stretch the bus access time. The EW bit does not apply to chip selects operating in LCD or PCMCIA mode because they have different wait mechanisms. R/W 0 R/W 0
54
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
Bits 6
Name H
Description Half Bus. Selects the data bus width for the chip select. 0 1 32-bit bus. 16-bit bus using bits 15:0 of the data bus.
R/W R/W
Default 0, except for mem_stcfg0 where the default value is determined by ROMSEL and ROMSIZE out of reset. See Table 9-1 on page 182. 0
For PCMCIA device type, clear this bit. For LCD device type, set this bit.
5
BS
Burst Size for Page Mode Accesses. Selects the burst size for page mode accesses. Valid only in page mode (PM=1). 0 1 4 beats 8 beats
R/W
4
PM
If the PM bit is set the chip select will operate in page mode. This allows quick access to sequential locations in memory. Page mode applies only to reads. See Section 3.2.6.1 "Page Mode Transfers" on page 70. If the RO bit is set the chip select will operate in read only mode. This will inhibit the generation of write cycles to the chip select. Any attempt to write to the address region controlled by a read only chip select will be ignored. Device type. Selects the type of device controlled by the static controller chip select. A list of device types and encodings is shown in Table 3-5 "Device Type Encoding" on page 55. Programming multiple chip selects as LCD or PCMCIA is illegal. Only one of each is supported.
R/W
0
3
RO
R/W
0
2:0
DTY
R/W
0 (SRAM), except for mem_stcfg0 where the default value is 3 (Flash).
Table 3-5. Device Type Encoding
DTY 0 1 2 3 4 5-7 Chip Select Function Static RAM I/O Device PCMCIA Device/Compact Flash Flash Memory LCD Device (RCS2# only) Reserved PFN[35:32] (upper nibble of physical address) 0x0 0xD 0xF 0x0 0xE Reference Section 3.2.2 on page 60 Section 3.2.2 on page 60 Section 3.2.3 on page 62 Section 3.2.2 on page 60 Section 3.2.4 on page 68
Table 3-6. Burst Size Mapping
Signal burst_size[2] burst_size[1] burst_size[0] Pin LWR0# LRD1# LRD0#
AMD AlchemyTM AU1500TM Processor Data Book
55
www..com
30361D Static Bus Controller
3.2.1.2 Static Timing Registers The static timing registers allow software to control the timing of each phase of a static bus access. The names of the timing parameters correspond directly to timing parameters shown on the timing diagrams. All timing parameters are expressed as a number of clock cycles. The base clock frequency is the SBUS clock. The actual number of clocks for each timing parameter (Tparameter) is shown in Table 3-7. Note that the timing behavior for Tcsh is different and is shown in Table 3-8.
Table 3-7. Actual Number of Clocks for Timing Parameters (Except Tcsh)
Device Type Static RAM, I/O, Flash PCMCIA Device/Compact Flash TS = 0 Tparameter + 1 Tparameter + 2 TS = 1 (4 * Tparameter) + 1 (4 * Tparameter) + 2
Table 3-8. Actual Number of Clocks for Tcsh
Tcsh Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TS = 0 3 3 6 6 6 9 9 9 12 12 12 15 15 15 18 18 TS = 1 3 6 12 15 18 24 27 30 36 39 42 48 51 54 60 63
56
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
mem_sttime0 (I/O, Flash, SRAM config) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Twcs Tcsh Twp Tcsw Def. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 mem_sttime1 (I/O, Flash, SRAM config) mem_sttime2 (I/O, Flash, SRAM and LCD config) mem_sttime3 (I/O, Flash, SRAM config) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Twcs Tcsh Twp Tcsw Def. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 1
87 Tpm 11
6 1
5 0
Offset = 0x1004 3210 Ta 11101 4 Offset = 0x1014 Offset = 0x1024 Offset = 0x1034 43210 Ta 11111
9 1
87 Tpm 11
6 1
5 1
Bits 31 30:28
Name -- Twcs
Description Reserved, should be cleared. This field specifies the required chip select hold time after a write pulse. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W R R/W
Default 0 0x3
27:24
Tcsh
Chip select hold-off. Specifies the minimum number of cycles that the chip select must remain inactive between accesses. The next transaction through the static bus controller is held off until the Tcsh parameter is satisfied. If this next access falls within another chip select's memory region, the new set of timing parameters associated with the controlling chip select take effect once the new transaction begins. Note that the SBUS can arbitrarily extend the time between accesses for internal operations. This can add up to about five additional clocks to the programmed time. See Table 3-8 "Actual Number of Clocks for Tcsh" on page 56 for the actual number of clock cycles.
R/W
0xF
23:20 19:14
-- Twp
Reserved, should be cleared. This field specifies the duration of the write enable. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R R/W
0 0x3F
13:10
Tcsw
Chip select to write. Defines the delay from the assertion of chip select until the write strobe and byte enables are asserted. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W
0xF
9:6
Tpm
This field determines the number of cycles required from a burst address change until read data is valid if the PM bit is set in the mem_stcfgn register. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles. Ta determines the access time for the first beat of each burst.
R/W
0xF
5:0
Ta
The Ta parameter determines the number of cycles required for the assertion of the chip select. For page mode accesses Ta determines the access time up to the first beat of each burst, or the first beat after a page mode wrap. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W
0x3F, except for mem_sttime0 where the default value is 0x1D.
AMD AlchemyTM AU1500TM Processor Data Book
57
www..com
30361D Static Bus Controller
mem_sttime0 (PCMCIA config) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Tmst Tmsu Tmih Def. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 mem_sttime1 (PCMCIA config) mem_sttime2 (PCMCIA config) mem_sttime3 (PCMCIA config) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Tmst Tmsu Tmih Def. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 1
87 Tist 11
6 1
5 0
Offset = 0x1004 3210 Tisu 11101 4 Offset = 0x1014 Offset = 0x1024 Offset = 0x1034 43210 Tisu 11111
9 1
87 Tist 11
6 1
5 1
Bits 31:24
Name Tmst
Description This field specifies the strobe width during memory accesses to PCMCIA chip selects. The timing duration depends on the time-scale option mem_stcfgn[TS]: When TS=0, (Tmst + 2) is the number of cycles to the end of the strobe; however, the read occurs at (Tmst + 1). When TS=1, [(4 * Tmst) + 2] is the number of cycles to the end of the strobe; however, the read occurs at [(4 * Tmst) + 1].
R/W R/W
Default 0xFF
23:17
Tmsu
This field specifies the setup time from chip select to strobe during memory accesses to PCMCIA chip selects. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W
0x7F
16:11
Tmih
This field specifies the hold time for address, data, and chip selects from the end of the strobe for both memory and I/O cycles to PCMCIA chip selects. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W
0x3F
10:5
Tist
This field specifies the strobe width for I/O accesses for a chip select configured for PCMCIA. The timing duration depends on the time-scale option mem_stcfgn[TS]: When TS=0, (Tmst + 2) is the number of cycles to the end of the strobe; however, the read occurs at (Tmst + 1). When TS=1, [(4 * Tmst) + 2] is the number of cycles to the end of the strobe; however, the read occurs at [(4 * Tmst) + 1].
R/W
0x3F, except for mem_sttime0 where the default value is 0x3E.
4:0
Tisu
This field specifies the setup time from chip select to strobe during I/O accesses for PCMCIA. See Table 3-7 "Actual Number of Clocks for Timing Parameters (Except Tcsh)" on page 56 for the actual number of clock cycles.
R/W
0x1F, except for mem_sttime0 where the default value is 0x1D.
58
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
3.2.1.3 Static Chip Select Address Configuration Registers (mem_staddrn) The static memory chip-select address configuration registers (mem_staddrn) assign an address range for each chip select. As shown below, each register contains a base address, an address comparison mask, and an enable bit.
mem_staddr0 - RCS0# Address Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 E CSBA Def. 0 0 0 Rs 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 mem_staddr1 - RCS1# Address Configuration mem_staddr2 - RCS2# Address Configuration mem_staddr3 - RCS3# Address Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 E CSBA Def. 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Offset = 0x1008 3210 1 1 1 1
9 1
765 CSMASK 1111
8
4 1
9 1
765 CSMASK 1111
8
Offset = 0x1018 Offset = 0x1028 Offset = 0x1038 43210 1 1 1 1 1
Bits 31:29 28
Name -- E
Description Reserved, should be cleared. Enable 0 1 Chip select is disabled. Chip select is enabled.
R/W R R/W
Default 0 0, except for mem_staddr0 (Note 1) 0x3FFF, except for mem_staddr0 where the default value is 0x7F0. 0x3FFF
27:14
CSBA
Chip select base address. Specifies bits 31:18 of the physical base address for this chip select. The upper nibble of the chip select address is determined by the device type selected in mem_stcfgn[DTY]. The lower bits of the base address are zeros.
R/W
13:0
CSMASK
Chip select address mask. Specifies bits 31:18 of the address comparison mask used to decode this chip select. (The upper nibble of the address comparison mask is determined by mem_stcfgn[DTY]. The lower bits of the mask are zeros.)
R/W
Note 1.
The enable (E) bits for chip selects RCS1#, RCS2#, and RCS3# are automatically cleared (disabled) coming out of a runtime or hardware reset. For RCS0#, however, the reset value of the E bit depends on ROMSEL: Holding ROMSEL low indicates that ROM should be used for the boot vector (and RCS0#'s E bit is set); otherwise, RCS0# is disabled. See also Section 9.3 "Boot" on page 182.
Once enabled, a chip select is asserted when the following condition is met: (phys_addr & addr_mask) == base_addr where: phys_addr: addr_mask: base_addr: 36-bit physical address output on the internal SBUS (from the TLB for memory-mapped regions) address comparison mask taken from CSMASK chip select base address taken from CSBA
Note that chip select regions must be programmed so that each chip select occupies a unique area of the physical address space. Programming overlapping chip select regions results in undefined operation.
AMD AlchemyTM AU1500TM Processor Data Book
59
www..com
30361D Static Bus Controller
3.2.2
Static RAM, I/O Device and Flash Device Types
This section describes the static RAM interface which is implemented when the device type (mem_stcfgn[DTY]) is programmed to 0, 1 or 3. (See Section 3.2.1.1 "Static Bus Configuration Registers" on page 54.) The static RAM, I/O device and Flash device types are all similar. The I/O device type is identical to the static RAM type except that it expects the upper nibble of the system address (bits [35:32]) to be 0xD. The only difference between the Flash device type and the static RAM device type is that the Flash timing allows for a chip select hold time after a write pulse using mem_sttimen[Twcs]. Other than these differences, the static RAM, I/O device and Flash device types share the same timing and control signals. The control signals are shown in Table 3-9.
Table 3-9. Static RAM, I/O Device and Flash Control Signals
Pin Name RAD[31:0] RD[31:0] RBE[3:0]# Input/Output O I/O O Description Address bus Data bus Byte enables: RBE0# corresponds to RD[7:0]. RBE1# is for RD[15:8]. RBE2# is for RD[23:16]. RBE3# is for RD[31:24]. RWE# ROE# RCS[3:0]# EWAIT# O O O I Write enable. Output enable. Programmable Chip Selects (4 banks). RCSn# is not used when configured as a PCMCIA device. Can be used to stretch the bus access time when enabled through mem_stcfgn[EW].
3.2.2.1 Static Memory Timing The following figures show static memory timing. Figure 3-4 on page 61 illustrates static memory read timing, and Figure 36 on page 61 illustrates static memory write timing. The EWAIT# timing diagrams are presented to show how EWAIT# will hold the cycle past Ta for reads and Twp for writes. Setup, hold, and delay timing specifications (electrical switching characteristics) are presented in Section 12.0 "Electrical and Thermal Specifications". (See Section 12.6.2 "Static Bus Controller Timing" on page 222.) Timing parameters do not take into account SBUS overhead which may add inter-access delays. These delays are dependent on system design and are affected by the number of bus masters and the ability of other devices to hold the bus.
60
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
Read Timing Read accesses to the static bus always retrieve 32-bits of data. As such, all four byte enables are asserted during the 32bit access or the two 16-bit beats. The control signals (RCSn#, ROE#, and RBE[1:0]#) span both accesses. The only signal that changes state to indicate the start of the second beat is RADDR[1].
Ta RCSn# Ta RBE[3:0]# RWE# ROE# RAD[31:0] RD[31:0] BurstSize[2:0]
addr1 addr2 addr2+4 addr2+8 addr2+12
Tcsh
Tpm
Tpm
Tpm
data1
data2a
data2b
data2c
data2d
Figure 3-4. Static Memory Read Timing (Single Read Followed by Burst)
Ta RCSn# ROE# EWAIT#
Figure 3-5. Static Memory Read EWAIT# Timing
Write Timing The timing diagrams below show the static bus write timing for I/O and SRAM device types. Figure 3-6 shows a single 32bit write on a 32-bit chip select.
Twcs RCSn# RBE[3:0]# Tcsw RWE# ROE# RAD[31:0] RD[31:0] addr1 data1 Twp
Figure 3-6. Static Memory Write Timing
Twcs RCSn# Twp RWE# EWAIT#
Figure 3-7. Static Memory Write EWAIT# Timing
AMD AlchemyTM AU1500TM Processor Data Book 61
www..com
30361D Static Bus Controller
3.2.3
PCMCIA/Compact Flash Device Type
Because of the similarity of Compact Flash and PCMCIA, references to PCMCIA should be taken as applicable to Compact Flash except where noted. The PCMCIA peripheral is designed to the PCMCIA2.1 specification--but only for the bus transactions as described in this section. The AU1500 processor provides a PCMCIA host adapter when the device type is programmed for PCMCIA. The static controller interface provides the required bus signals necessary to control a PCMCIA interface. Auxiliary signals, such as card detect and voltage sense, can be implemented with GPIOs if desired. The PCMCIA host interface adapter will support memory, attribute and I/O transactions. External logic can be added to support DMA transfers. The AU1500 processor supports only 8- and 16-bit load and store instructions (byte and halfword instructions) to PCMCIA devices. 32-bit accesses are not supported. The PCMCIA interface provides control signals defined for PCMCIA devices. If two devices are required then external logic must be added to allow for both cards to share the bus. Note that when a chip select is programmed as a PCMCIA device that the associated RCSn# is not used. The PCMCIA interface occupies a 36-bit address space with the upper 4 bits equal to 0xF. The TLB is required to generate addresses that will activate a chip select with a device type of "PCMCIA". I/O, Memory and Attribute spaces are differentiated by addr[31:30]. Table 3-10 shows the mapping.
Table 3-10. PCMCIA Memory Mapping
Physical Address 0xF 0xxx xxxx 0xF 4xxx xxxx 0xF 8xxx xxxx PCMCIA Mapping I/O Attribute Memory Memory
Note:
Each of the PCMCIA physical address spaces have a maximum size of 64 MBytes. Any access beyond the 64MByte space will alias back into the defined region.
Table 3-11 enumerates the signals to support the PCMCIA interface.
Table 3-11. PCMCIA Interface Signals
Pin Name RAD[31:0] RD[15:0] PREG# PCE[2:1]# POE# PWE# PIOR# PIOW# PWAIT# Input/Output O I/O O O O O O O I Description Address Bus. Data Bus. When this signal is asserted card access is limited to attribute memory when a memory access occurs and to I/O ports when an I/O access occurs. Card Enables. Memory Output Enable. Memory Write Enable. I/O Read Cycle Indication. I/O Write Cycle Indication. This signal is asserted by the card to delay completion of a pending cycle. Note that this signal should be tied high through a resistor when the PCMCIA interface is not used. PIOS16# ROE# I O 16-bit port select. Note that this signal should be tied high through a resistor when the PCMCIA interface is not used. Output Enable - This output enable is intended to be used as a data transceiver control. During a PCMCIA transaction, ROE# remains asserted (low) as configured in the timing registers (mem_sttimen) for reads and negated (high) for writes.
62
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
Figure 3-8 and Figure 3-9 on page 64 show a one and two card PCMCIA implementation. For the two card implementation RAD26 is used as a card select signal. Both figures assume that the PCMCIA card can be hot swapped at any time--note the use of isolation buffers on the shared bus. If the card is fixed in the system much of the interface logic can be removed. A Compact Flash implementation is very similar to the PCMCIA implementation except that the number of address lines used is fewer.
RD[15:0]
16-bit transceiver with bus hold OE# DIR PCE1# PCE2#
PCMCIA Slot 0
ROE# PCE[2:1]# RAD[25:0] PREG# POE# PWE# PIOR# PIOW# CE[2:1]# ADDR[25:0] REG# OE# WE# IOR# IOW# IOIS16#
AU1500TM Processor PCMCIA Host Adapter
Buffer OE# DETO#
PIOS16#
PWAIT#
WAIT# RDY/BSY#
GPIO[w]
GPIO[y]
DETO# (If an extra GPIO is available, this gate can be eliminated.)
CD1# CD2#
Figure 3-8. One Card PCMCIA Interface
AMD AlchemyTM AU1500TM Processor Data Book
63
www..com
30361D Static Bus Controller
RD[15:0]
16-bit transceiver with bus hold OE# DIR S0CE1# S0CE2# S1CE1# S1CE2# 16-bit transceiver with bus hold OE# DIR
PCMCIA Slot 0 PCMCIA Slot 1
ROE# RAD[25:0] PREG# POE# PWE# PIOR# PIOW# 32-bit Buffer OE# DETO# 32-bit Buffer OE# DETO# ADDR[25:0] REG# OE# WE# IOR# IOW#
ADDR[25:0] REG# OE# WE# IOR# IOW#
AU1500TM Processor PCMCIA Host Adapter
PCE1# PCE2#
S0CE1#
CE1#
S0CE2#
CE2#
S1CE1#
CE1#
S1CE2# RAD26 WAIT#
CE2#
PWAIT#
WAIT#
PIOS16#
0 1
IOIS16# IOIS16# RAD26
GPIO[w] GPIO[x] GPIO[y] GPIO[z] DETO#
RDY/BSY# RDY/BSY# CD1# CD2# CD1# CD2#
DETO#
Figure 3-9. Two Card PCMCIA Interface
64
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
3.2.3.1 PCMCIA/CompactFlash Interface The figures on the following pages illustrate the functional timing of the PCMCIA interface, including memory read timing, memory write timing, I/O read timing, and I/O write timing. The PWAIT# timing diagrams are presented to show how PWAIT# will hold the cycle past Tmst for memory reads and writes and Tist for I/O reads and writes. Setup and hold time requirements are presented in Section 12.6.2 "Static Bus Controller Timing" on page 222.
Tmih
PCE[2:1]# PREG# Tmsu POE# ROE# PWE# PIOR# PIOW# PIOS16# PWAIT# RAD[31:0] RD[15:0] read data Tmst
Tmih
Figure 3-10. PCMCIA Memory Read Timing
Tmih PCE[2:1]# Tmst POE# PWAIT#
Figure 3-11. PCMCIA Memory Read PWAIT# Timing
AMD AlchemyTM AU1500TM Processor Data Book
65
www..com
30361D Static Bus Controller
Tmih PCE[2:1]# PREG# POE# Tmsu PWE# PIOR# PIOW# PIOS16# PWAIT# RAD[31:0] RD[15:0] write data Tmst
Figure 3-12. PCMCIA Memory Write Timing
PCE[2:1]# Tmst PWE# PWAIT#
Tmih
Figure 3-13. PCMCIA Memory Write PWAIT# Timing
PCE[2:1]# PREG# POE# PWE# Tisu PIOR# PIOW# PIOS16# PWAIT# RAD[31:0] RD[15:0] read data Tist
Tmih
Figure 3-14. PCMCIA I/O Read Timing
66
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
PCE[2:1]# Tist PIOR# PWAIT#
Tmih
Figure 3-15. PCMCIA I/O Read PWAIT# Timing
PCE[2:1]# PREG# POE# PWE# PIOR# Tisu PIOW# PIOS16# PWAIT# RAD[31:0] RD[15:0]
write data
Tmih
Tist
Figure 3-16. PCMCIA I/O Write Timing
PCE[2:1]# Tist PIOW# PWAIT#
Tmih
Figure 3-17. PCMCIA I/O Write PWAIT# Timing
AMD AlchemyTM AU1500TM Processor Data Book
67
www..com
30361D Static Bus Controller
3.2.4
LCD Controller Device Type
The AU1500 processor provides a LCD controller host adapter when the device type is programmed for an LCD. The static controller interface provides the bus signals necessary to interface to most LCD controllers. A dedicated clock LCLK is provided for the LCD interface. The LCLK rate is the SBUS rate divided by a factor programmed in mem_stcfg0[D5]; see Section 3.2 "Static Bus Controller" on page 53. The AU1500 supports 8-, 16-, and 32-bit load and store instructions (byte, halfword, and word instructions) to the LCD controller interface. The LCD controller occupies 36-bit address space with the upper 4 bits equal to 0xE. The MMU is required to generate addresses that will generate a chip select with a device type of "LCD". Table 3-12 lists the control signals to support the LCD controller.
Table 3-12. LCD Controller Interface Signals
Signal RAD[31:0] RD[15:0] RCS[3:0]# LCLK LWAIT# LRD[1:0]# LWR[1:0]# Input/Output O I/O O O I O O Function Address Bus. Data Bus. Chip Selects. Interface Clock. Extend Cycle. Read Indicators. Write Indicators.
68
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
3.2.5
LCD Controller Interface Timing
The following figures shows the LCD timing. The LWAIT# timing diagrams are presented to show how LWAIT# will hold the cycle past Ta for memory reads and Twp for memory writes. LWAIT# timing requirements as well as setup and hold times are presented in Section 12.6.2 "Static Bus Controller Timing" on page 222.
LCLK RAD[31:0] RCSn# LRD[1:0]# Tcsh LWR[1:0#] Tcsw RD[15:0] input output Twp Ta Twch
Figure 3-18. LCD Controller Timing
RCSn# Ta LRD[1:0#] LWAIT#
Figure 3-19. LCD Read LWAIT# Timing
Twcs RCSn# Twp LWR[1:0] LWAIT#
Figure 3-20. LCD Write LWAIT# Timing
AMD AlchemyTM AU1500TM Processor Data Book
69
www..com
30361D Static Bus Controller
3.2.6
Static Bus Controller Programming Considerations
3.2.6.1 Page Mode Transfers The static bus controller provides a page mode for quick read access to sequential locations in memory. Setting mem_stcfgn[PM] selects page mode operation for the chip select. The burst size (4 or 8 beats) for page mode transfers is programmed in mem_stcfgn[BS]. Depending on the speed of the external memory device, the system designer can adjust two timing parameters in mem_sttimen for page mode transfers: * Ta is the time from chip select assertion to the first beat of valid data. Ta is the time required for the initial access to a peripheral device. Ta must allow time for the peripheral device to load its read buffer or activate the next page. Note that the page size depends on the peripheral device. * Tpm is the time between beats. Figure 3-4 "Static Memory Read Timing (Single Read Followed by Burst)" on page 61 shows an example page mode read with the timing parameters Ta and Tpm. The static bus controller does not check for page boundaries during page mode reads. The addressing is sequential regardless of alignment. An access which crosses a page boundary may return invalid data if Tpm does not allow enough time for the external memory device to update its read buffer or activate the next page. If the system designer cannot ensure adequate address alignment to avoid crossing page boundaries, Tpm must be long enough to accommodate potential page updates. In general, page-boundary timing issues do not arise for instruction fetches because they are always accessed first-wordfirst and therefore are properly aligned. Data fetches, however, may have page-boundary timing issues because they are accessed critical-word-first unless CCA=4 (fetch the first-word first). Note that EWAIT# can delay only the start of the burst (extend the Ta timing). That is, EWAIT# cannot be used to account for varying timing between beats (extend the Tpm timing) that may occur even for transfers within a page. Halfword Ordering and 16-bit Chip Selects Because the static bus controller is not aware of the endian mode of the Au1 core, potential halfword swapping conflicts can arise. Upon reset, chip selects default to little-endian byte ordering (mem_stcfg[BE] = 0). Figure 3-21 on page 70 shows the data formats for the 32-bit SBUS and for a little-endian 16-bit chip select. 31 32-Bit SBUS Format A 24 23 B 2 AB Big Endian Offset 0 2 CD 16 15 C 87 D 0 Little Endian Offset 0
15 C 16-Bit Static Bus Little-Endian Format A
87 D B
0 Physical Offset 0 Physical Offset 2
Figure 3-21. 16-Bit Chip Select Little-Endian Data Format (Default)
70
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Static Bus Controller 30361D
When a 16-bit chip select is in little-endian mode, the static bus controller accesses the least-significant halfword CD at physical offset 0 and accesses the most-significant halfword AB at physical offset 2. When the Au1 core is also in littleendian mode, the requested Au1 core offsets match the physical offsets of the 16-bit device. That is, the static bus controller and the Au1 core have the same view of memory. However, when the processor core is in big-endian mode, the default ordering of the static bus controller effectively reverses the ordering of the halfwords from what the big-endian Au1 core expects, as shown in Figure 3-22.
31 32-Bit SBUS Format A
24 23 B
16 15 C 2
87 D 0 CD
0
Little Endian Offset
AB Big Endian Offset 0 2
Processor Big-Endian Offset 0 2 4 6 8 10
15 A C A C A C
87 B D B D B D
0
Device Physical Offset 2 0 6 4 10 8
Figure 3-22. Big-Endian Au1 Core and Little-Endian 16-Bit Chip Select
AMD AlchemyTM AU1500TM Processor Data Book
71
www..com
30361D Static Bus Controller
For RAM memories, the halfword swapping has no side-effects because reads and writes are consistent. However, for ROM, Flash memories, and peripherals, be aware of the following side effects: * For ROM and Flash, the memory contents are halfword-swapped throughout the entire 16-bit device memory. * For Flash and peripherals, the programming register offsets are also halfword-swapped. To prevent halfword swapping, configure the chip select for big-endian mode (mem_stcfg[BE] = 1) before accessing the memory. (If booting from static memory, see Section 9.3.1 "Endianness and 16-Bit Static Bus Boot" on page 182.) The static bus controller inverts RAD1 for transfers on 16-bit chip selects in big-endian mode, as shown in Figure 3-23 on page 72.
31 32-Bit SBUS Format A
24 23 B
16 15 C 2
87 D
0
0 CD 2
Little Endian Offset
AB Big Endian Offset 0
Processor Big-Endian Offset 0 2 4 6 8 10
15 A C A C A C
87 B D B D B D
0 Device Physical Offset 0 2 4 6 8 10
Figure 3-23. Big-Endian Au1 Core and Big-Endian 16-Bit Chip Select
72
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
4.0PCI 2.2 Bus Controller
The AU1500 processor contains a PCI 2.2 compliant controller to allow connection of external peripherals. The PCI bus may be operated at 33 or 66 MHz. The PCI clock can be driven by the AU1500 processor or by an external source. Only 32bit wide operation is supported. The controller is capable of both executing processor initiated master transactions to PCI and accepting external PCI target transactions to the AU1500 processor's local memory.
4
The PCI controller can operate as either a host or satellite subsystem. When operating as a host, all PCI system configuration is done by the AU1500, and the PCI header space is not visible from the PCI bus. When operating as a satellite, PCI header space is only accessible by an external host, not by the AU1500 processor core. The AU1500 configuration registers are only visible from the processor in both host and satellite mode. The pin PCI_CFG determines whether the AU1500 processor operates as a host or a satellite. The PCI controller contains an internal arbiter for five PCI devices including the AU1500 processor itself. This allows a glueless interface for up to four external PCI devices. The internal arbiter may be disabled if an external arbiter is desired. The PCI controller contains 4 data FIFOs to enhance performance to and from PCI. These FIFOs are sized to minimize stalls and increase the System Bus (SBUS) efficiency during PCI bus transactions.
4.1
PCI Memory Map
Table 4-1 shows the location of PCI interface elements within the AU1500 memory map. Note that the addresses shown are 36-bit physical addresses. It is necessary to use the MMU to generate addresses to access PCI areas with the exception of the cacheable memory window, AU1500 processor configuration registers, and PCI header space.
Table 4-1. PCI Memory Map
Physical Address 0x0 1400 50xx 0x0 1400 51xx 0x4 xxxx xxxx 0x5 xxxx xxxx 0x6 xxxx xxxx Function AU1500 Configuration Registers PCI Header Space PCI Non-cacheable Memory Space PCI I/O Space PCI External Configuration Space
A window within the first 4 GB can be configured to access cacheable PCI memory space. This window is configured using the pci_cmem register. Accesses to the PCI Non-cacheable Memory, I/O, and External Configuration spaces will cause memory, I/O, or configuration cycles to be run on PCI respectively. The lower 32 bits of the 36-bit address are reflected on the PCI bus for these transactions. The AU1500 can generate both Type 0 and Type 1 configuration cycles. Setting physical address bit [31] when accessing PCI external configuration space will generate a Type 1 configuration cycle. Clearing this bit will generate a Type 0 configuration cycle. On the PCI bus, bit [31] will be 0 for both Type 0 and Type 1 configuration cycles.
AMD AlchemyTM AU1500TM Processor Data Book
73
www..com
30361D PCI 2.2 Bus Controller
4.1.1
Local PCI Configuration Register Block
Table 4-2 shows the register map for the AU1500 processor local configuration register block. The upper 256 bytes map to the PCI configuration header space defined by the PCI specification. When the PCI controller is configured to operate in satellite mode, the PCI header space is not accessible through the AU1500 PCI configuration space. In satellite mode, the PCI header space is accessible through external PCI configuration cycles. When the PCI controller is configured to operate in host mode, the PCI header space is not accessible via PCI by external devices. All appropriate configuration registers in the lower 256 bytes of the address map, the AU1500 processor configuration registers, must be written to the appropriate values before writing the upper registers or configuring the system in either Host or Satellite mode. In Host mode, all configuration registers must be written before accessing external devices.
Table 4-2. PCI Bus Controller Configuration Registers
Offset from 0x0 1400 5000 (Physical) 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x100 0x104 0x108 0x10C 0x110 0x140 Register Name pci_cmem pci_config pci_b2bmask_cch pci_b2bbase0_venid pci_b2bbase1_subid pci_mwmask_dev pci_mwbase_rev_ccl pci_err_addr pci_spec_intack pci_id pci_statcmd pci_classrev pci_param pci_mbar pci_timeout Description PCI Cacheable Memory Region Register Configuration/Error Register Back-to-Back Mask/Class Code High Register Back-to-Back Base 0/Vendor ID Register Back-to-Back Base 1/Subsystem ID Register MBAR Address Mask/Device ID Register MBAR Window Base/Revision/Class Code Low Register PCI Error Address Register PCI Special/Int Ack Cycle Register Device and Vendor ID Register Status and Command Register Class and Revision Code Parameter Register (BIST, header type, latency timer, cache line size) Memory Base Address Register (MBAR) Timeout Register
74
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
4.1.1.1 PCI Cacheable Memory Region Register The pci_cmem register configures the location of the cacheable memory window to PCI memory space. This allows processor initiated burst memory reads and writes to the PCI bus. Note that when the cacheable memory window is enabled, it must be mapped to CCA encoding 4. A cacheable memory window size of 256 KB to 2 GB is supported. A PCI memory transaction is executed when the following condition is met: (physical_addr[31:18] & cm_mask) == cm_base Bits [13:0] is the cacheable memory mask. Bits [27:14] is the base address of the cacheable memory region. Bit [28] is the cacheable memory enable.
pci_cmem - PCI cacheable memory region Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 E CM_BASE Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000 3210 0 0 0 0
9 0
765 CM_MASK 0000
8
4 0
Bits 31:29 28
Name -- E
Description Reserved, should be cleared. Enable. 0 1 Disable PCI cacheable memory. Enable PCI cacheable memory.
R/W R R/W
Default 0 0
27:14 13:0
CM_BASE CM_MASK
Specifies bits [31:18] of the starting/base address for the PCI cacheable memory region Specifies which bits of physical_addr[31:18] are used to decode the PCI cacheable memory region.
R/W R/W
0x0 0x0
4.1.1.2 PCI Configuration/Error Register The pci_config register configures the general operation of the PCI interface. It allows configuration of the AU1500 on-chip arbiter, interrupt generation, and improved error reporting. Bits [31:28] are the upper error address of the PCI Error Address register. Bits [27:22] determine what conditions were present during an error; see Section 4.3.6 "PCI Errors" on page 83 for further discussion. These bits can be used in conjunction with the PCI Status register defined in the PCI 2.2 specification. Bit [19] enables byte masking for byte and halfword reads from memory or the configuration space. Note that if BME (bit 19) is not set, reads less than 32 bits from these areas are not supported. Bit [16] is the non-cacheable bit. If set, all PCI master initiated accesses to the AU1500 memory space will be run as noncacheable. The default is for all accesses to be marked cacheable on the AU1500 SBUS. Bits [13:8] are the PCI interrupt mask. If a bit is a zero, the appropriate condition will not assert the PCI interrupt. This mask can be used to assist debug by only interrupting on specific conditions. Bits [7:4] are used to control address/data manipulation for big endian support. Refer to Section 4.3.8 "Endian Support" on page 84 for a detailed functional description of these bits. Bits [3:0] configure and enable the on-chip arbiter.
pci_config - PCI configuration/error Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR_ADDR ERD ET EF EP EM BM PD BME NC IA IP IS
9 0
8 0
7
SIC
6 0
5
ST
4 0
Offset = 0x004 3210 0 0 0 0
IMM ITM ITT IPB
SM AEN R2H R1H CH
Def. 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Bits 31:28 27
Name EA[35:32] ERD
Description These bits are the upper 4 bits of the error address register. PCI error occurred on a read/write#. If an error is detected for a PCI access, ERD reflects the direction of the transaction. 0 1 Error occurred on a write. Error occurred on a read.
R/W R/W R/W
Default 0 0
26 25
ET EF
PCI error occurred while the AU1500 was a target. PCI fatal error detected. These errors include Master and Target Aborts as well as certain errors not specified in the PCI Specification, but which may be important to the user.
R/W R/W
0 0
AMD AlchemyTM AU1500TM Processor Data Book
75
www..com
30361D PCI 2.2 Bus Controller
Bits 24
Name EP
Description PCI parity error detected. Parity errors are detected either by the AU1500 bus interface on data it receives, or by the target device on the PCI bus and passed to the AU1500 via PCI_PERR#. Multiple PCI errors detected. If an error was detected while EF or EP is asserted, EM is set. PCI Arbiter detected bad master--does not assert PCI_FRAME# (or negate PCI_REQn#) within 16 clocks of being granted the PCI bus. Reserved, should be cleared. PCI Disable. When this bit is set the PCI controller responds to target accesses with a PCI RETRY. Byte mask enable for reads. This bit applies only to 8- and 16-bit read accesses to memory and the configuration space. (The appropriate byte lane masking is automatically applied for I/O reads less than 32 bits. Also, writes of any length and destination always have appropriate byte lane masking.) 0 1 Do not apply byte lane masking during 8-, 16-bit reads. (All byte enables are asserted regardless of transaction size.) Mask the appropriate byte lanes during 8-, 16-bit reads.
R/W R/W
Default 0
23 22 21 20 19
EM BM -- PD BME
R/W R/W R R/W R/W
0 0 0 1 0
18:17 16 15
-- NC IA
Reserved, should be cleared. Target accesses to AU1500 memory are marked as non-coherent if this bit is set. PCI_INTA# Enable. This bit is reflected in bit 8 of offset 0x3C in configuration space. If the AU1500 can generate a PCI interrupt this bit should be set. Reserved, should be cleared. Assert the interrupt signal back to the interrupt controller if PCI_PERR# is detected. This is bit 15 of the status register in PCI space. Assert the interrupt signal back to the interrupt controller if a PCI_SERR# is generated. This is bit 14 of the status register in PCI space. Assert the interrupt signal back to the interrupt controller if a Master-Abort is asserted and the AU1500 processor is the master. This is bit 13 of the status register in PCI space. Assert the interrupt signal back to the interrupt controller if a Target-Abort is detected while the AU1500 processor is a Master. This is bit 12 of the status register in PCI space. Assert the interrupt signal back to the interrupt controller if a Target-Abort is asserted and the AU1500 is the Target. This is bit 11 of the status register in PCI space. Assert the interrupt signal back to the interrupt controller if a PCI_PERR# is detected, the AU1500 is the bus master and the perr_enable bit is set in PCI configuration space. This is bit 8 of the status register in PCI space. These bits determine the address and data swapping of I/O and Configuration cycles initiated by the AU1500 to/from external devices. Please refer to Section 4.3.8 "Endian Support" on page 84 for a detailed description of these bits. Swap data on PCI target transactions initiated by external PCI devices to/ from AU1500 memory. Swap data on AU1500 processor initiated master memory transactions to/ from PCI. When set this bit enables the AU1500 internal arbiter. When set, PCI_REQ2# arbitrates into the high priority arbiter. When set, PCI_REQ1# arbitrates into the high priority arbiter. When set, the AU1500 processor arbitrates into the high priority arbiter.
R R/W R/W
0 0 0
14 13 12 11
-- IP IS IMM
R R/W R/W R/W
0 0 0 0
10
ITM
R/W
0
9
ITT
R/W
0
8
IPB
R/W
0
7:6
SIC
R/W
0
5 4 3 2 1 0
ST SM AEN R2H R1H CH
R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0
76
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
PCI Back-to-Back Mask/Class Code High, Base0/PCI Subsystem Vendor ID, and Base1/PCI Subsystem ID Registers Master initiated fast back-to-back transfers require that the subsequent access is to the same target as the previous access. The AU1500 processor allows the programmer to set up two target back-to-back windows. The Mask Register configures the size of the windows, while the base registers set the base address of each target window. A fast back-to-back transaction is attempted when ((physical_addr & b2b_mask == b2b_base0) | (physical_addr & b2b_mask == b2b_base1)). Fast back-to-back is enabled by setting bit 9 of the pci_statcmd register which is at offset 0x104 in the PCI Configuration space. The lower 16 bits of the Fast Back-to-Back Mask register sets the Class Code High field. This field is the upper 16 bits of the Class Code defined by the PCI 2.2 specification. It is combined with the Class Code Low field to form the full 24-bit Class Code. This field can be written from the processor only and are reflected out to the PCI bus on configuration read cycles to address 0x08 when the AU1500 is configured as a satellite. The lower 16 bits of the Fast Back-to-Back Base0 register sets the Subsystem Vendor ID, and the lower 16 bits of the Fast Back-to-Back Base1 register is the Subsystem ID. These fields can be written from the processor only, and allow for identification of different systems which contain an AU1500. These fields are reflected out to the PCI bus on configuration read cycles to address 0x2C when the AU1500 is configured as a satellite.
pci_b2bmask_cch - PCI back-to-back mask/class code high Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 B2BMASK Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x008 3210 0 0 0 0
4.1.1.3
9 0
87 CCH 00
6 0
5 0
4 0
Bits 31:16 15:0
Name B2BMASK CCH
Description This field is the mask used to qualify fast back-to-back transfers. Class Code High. These bits are reflected as the upper two bytes of the class code field in PCI configuration register space.
R/W R/W R/W
Default 0 0
pci_b2bbase0_venid - PCI back-to-back base Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 B2BBASE0 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
87 SVID 00
6 0
5 0
4 0
Offset = 0x00C 3210 0 0 0 0
Bits 31:16 15:0
Name B2BBASE0 SVID
Description This field specifies a base address for fast back-to-back transfers. This field is reflected as the subsystem vendor ID in PCI configuration space.
R/W R/W R/W
Default 0 0
pci_b2bbase1_subid - PCI back-to-back base Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 B2BBASE1 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
876 SUBID 0000
9
5 0
4 0
Offset = 0x010 3210 0 0 0 0
Bits 31:16 15:0
Name B2BBASE1 SUBID
Description This field specifies a base address for fast back-to-back transfers. This field is reflected as the subsystem ID in PCI configuration space.
R/W R/W R/W
Default 0 0
AMD AlchemyTM AU1500TM Processor Data Book
77
www..com
30361D PCI 2.2 Bus Controller
4.1.1.4 PCI Memory Window Mask/Device ID and Base/Revision/Class Code Low Registers The AU1500 processor allows PCI masters access to a window into memory. This window can be sized from 64 KB to 2 GB. The Memory Window Mask register configures the size of the memory window visible from the PCI bus. The Memory Window Base register configures the location of the memory window visible from the PCI bus. This allows a mapping from the PCI address to memory address. If a one to one mapping is required, the Memory Window Base register should be written with the same value as the Memory Base Address register which is located at offset 0x110 of the PCI Configuration space in Host mode. An external PCI access hits in the memory window when (pci_addr & mwmask == pci_mbar). The physical address to the AU1500 memory system becomes ((pci_addr & mwmask#) | mwbase). The lower 16 bits of the Memory Window Mask register is the Device ID field as defined by the PCI 2.2 specification. This field can be written from the processor only and is reflected out to the PCI bus on configuration read cycles to address 0x00 when the AU1500 is configured as a satellite. The lower 8 bits of the Memory Window Base register is the Class Code Low field. This field is the lower 8 bits of the Class Code defined by the PCI 2.2 specification. It is combined with the Class Code High field to form the full 24 bit Class Code. This field can be written from the processor only and are reflected out to the PCI bus on configuration read cycles to address 0x08 when the AU1500 processor is configured as a satellite. Bits [15:8] of the Memory Window Base register is the Revision ID field as defined by the PCI 2.2 specification. This field can be written from the processor only and is reflected out to the PCI bus on configuration read cycles to address 0x00 when the AU1500 is configured as a satellite.
pci_mwmask_dev - PCI memory window mask/device ID Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MWMASK Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x014 3210 0 0 0 0
876 DEVID 0000
9
5 0
4 0
Bits 31:16 15:0
Name MWMASK DEVID
Description This field sets the mask used to qualify target accesses to the PCI visible memory window. This field is reflected as the device ID in PCI configuration space.
R/W R/W R/W
Default 0 0
pci_mwbase_rev_ccl - PCI memory window base/revision/class code low Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MWBASE REVID Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
Offset = 0x018 43210 CCL 00000
Bits 31:16 15:8 7:0
Name MWBASE REVID CCL
Description This field sets the base address used to qualify target accesses to the PCI visible memory window. This field is reflected as the revision ID in PCI configuration space. These bits are reflected as the low byte of the class code field in PCI configuration space.
R/W R/W R/W R/W
Default 0 0 0
78
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
4.1.1.5 PCI Error Address Register This register captures error addresses on target writes, master reads and master writes. The upper 4 bits of the address are captured in the PCI Configuration/Error register. This address is intended to be used in conjunction with the PCI header error bits described in the PCI 2.2 specification. The error address captured is valid when the EF or EP bit is set in the Configuration/Error register. The address for target write errors may not be the specific identical error address due to synchronization issues. If multiple errors occur, this register contains the address of the first error.
pci_err_addr - PCI error address Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ERRADDR Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x01C 3210 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4 0
4.1.1.6 PCI Special/Int Ack Register This register allows the programmer to initiate special and interrupt acknowledge cycles on the PCI bus. A read to this register invokes an interrupt acknowledge cycle, and a write executes a special cycle. The register value read is undefined and the actual value written is ignored.
pci_specintack Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SPECINTACK[31:0] Def. x x x x x x x x x x x x x x x x x x x x x x Offset = 0x0020 3210 x x x x
9 x
8 x
7 x
6 x
5 x
4 x
4.1.2
PCI Visible Configuration Registers
The following registers are defined in PCI Local Bus Specification, revision 2.2. These registers are visible from the PCI bus as configuration space when the AU1500 is operating in satellite mode. When the AU1500 processor is operating in host mode these registers are available in the local configuration register block. For detailed description of these registers and their fields please refer to PCI Local Bus Specification, revision 2.2. The offsets given in the register descriptions below are the offsets within the AU1500 local configuration register block. The offset in the PCI configuration space is given by the PCI specification. 4.1.2.1 PCI Device/Vendor ID Register The pci_id register is defined in the PCI 2.2 specification. This register is visible at offset 0x00 in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode, this register is available at offset 0x100 of the PCI local configuration space.
pci_id - PCI configuration device/vendor ID Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DID Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Offset = 0x0100 3210 0 1 0 1
9876 VID = 0x1755 1101
5 0
4 1
4.1.2.2 PCI Status and Command Register The pci_statcmd register is defined in the PCI 2.2 specification. This register is visible at offset 0x04 in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode and also again in satellite mode, this register is available at offset 0x104 of the PCI local configuration space.
pci_statcmd - PCI configuration status/command Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STATUS Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0104 3210 0 0 0 0
9 0
87 CMD 00
6 0
5 0
4 0
4.1.2.3 PCI Class and Revision Register The pci_classrev register is defined in the PCI 2.2 specification. The CLASS field is constructed by concatenating the class code high and class code low fields in the local configuration block. This register is visible at offset 0x08 in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode, this register is available at offset 0x108 of the PCI local configuration space.
pci_classrev - PCI configuration class code/revision Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLASS Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0108 43210 REV 00000
9 0
8 0
7 0
6 0
5 0
AMD AlchemyTM AU1500TM Processor Data Book
79
www..com
30361D PCI 2.2 Bus Controller
4.1.2.4 PCI Parameter Register The pci_param register is defined in the PCI 2.2 specification. This register is visible at offset 0x0C in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode, this register is available at offset 0x10C of the PCI local configuration space.
pci_param - PCI configuration parameters Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BIST HT LT Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x010C 43210 CLS 00000
9 0
8 0
7 0
6 0
5 0
4.1.2.5 PCI Memory Base Register The pci_mbar register configures the PCI address base of the window into the AU1500 processor memory space. The pci_mbar register is defined in the PCI 2.2 specification. This register is visible at offset 0x10 in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode, this register is available at offset 0x110 of the PCI local configuration space.
pci_mbar - PCI configuration memory base address Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MBA Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0110 3210 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4 0
4.1.2.6 PCI Timeout Register The pci_timeout register specifies the maximum number of attempted retries per transaction and the maximum time spent waiting for a target to be ready for a transfer. The pci_timeout register is defined in the PCI 2.2 specification. This register is visible at offset 0x40 in configuration header space from the PCI bus when the device is configured to operate in satellite mode. In host mode, this register is available at offset 0x140 of the PCI local configuration space.
pci_timeout - PCI configuration timeout Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MR Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Offset = 0x0140 43210 TO 00000
9 0
8 0
7 1
6 0
5 0
Bits 31:16 15:8
Name -- MR
Description Reserved. Max retries. Contains the maximum number of retries to be attempted per transaction. Valid values range from 1 to 255. Note that a value of 0 disables this function, which means no limit is placed on the number of retries attempted. Target-ready (PCI_TRDY#) timeout. Contains the maximum number of PCI clocks to wait for PCI_TRDY# assertion before terminating a transfer. Valid values range from 1 to 255. Note that a value of 0 disables this function, which means no time limit is placed on waiting for PCI_TRDY#.
R/W R/W R/W
Default 0 0x80
7:0
TO
R/W
0x80
4.1.3
Accesses to Processor Memory from PCI
The AU1500 processor supports one memory window visible from the PCI bus. This memory window can be configured to a minimum size of 64 KB and a maximum size of 2 GB. The PCI address base of the window is set in the pci_mbar register. The location of the window within the AU1500 address space is configured in the pci_wbase register. The size is configured in the pci_wmask register. Only static memory accesses and SDRAM memory accesses are supported from PCI. Accesses to AU1500 processor peripherals and non-prefetchable external devices on the static interface are not supported. Also, all reads from AU1500 memory initiated from PCI will be prefetched. The AU1500 processor cache will snoop accesses to cacheable memory from PCI if the NC bit is clear in the PCI Configuration/Error register and substitute cache contents when a hit occurs. By locking an area of memory into the cache it is possible to transfer information to and from PCI without causing external memory cycles.
80
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
4.2
PCI Arbiter
The AU1500 contains an on-chip PCI arbiter. This arbiter supports 4 external devices and can be disabled if the use of an external arbiter is desired. When the on-chip arbiter is enabled, the AU1500 processor has four request inputs and four grant outputs. When an external arbiter is used, the input PCI_REQ0# is re-defined to be PCI_GNT0#, and the output PCI_GNT0# is re-defined to be PCI_REQ0#. The other request/grant signals are unused when an external arbiter is used. A two-level fair algorithm scheme is implemented, which ensures each master access to the bus independent of other requests. The two levels of arbitration allows bus masters to be assigned high or low priority according to their need to use the bus. Bus masters with a greater need to use the bus should be assigned to the high priority arbiter versus the low priority arbiter. As a group, the low priority requests will arbitrate into the high priority arbiter. In this way, high-priority bus masters cannot dominate the bus to the point of excluding low-priority masters which are continually requesting the bus. Two of the external master's and the AU1500 are configurable for high/low priority. The other two external masters are tied to either a fixed high or low priority, as shown in Table 4-3. Priorities should be initialized by software before masters begin to request use of the bus.
Table 4-3. PCI Arbiter Priority Configuration
Master External Master 3 External Master 2 External Master 1 External Master 0 AU1500 Priority High Priority pci_config[2] pci_config[1] Low Priority pci_config[0]
The arbiter implements bus parking so that when no other masters are requesting the use of the bus, the last master to have ownership of the bus retains that ownership until another request is received. Out of system reset, the AU1500 processor is the default owner and assumes responsibility for driving the PCI address bus, C/BE bus and PAR. This ensures that no excess current is drawn due to floating nodes. If a master receives a grant by requesting the bus and does not initiate a transaction within 16 PCI clocks after receiving the grant, the master is assumed to be broken and an error is reported to the bus controllers' PCI configuration/error register, pci_config[22].
4.3
Implementation Specifics
The following sections describe AU1500 implementation specific issues.
4.3.1
PCI Clock Generation
The AU1500 processor provides the capability to internally generate a clock on the PCI clock output pin (PCI_CLKO). For systems where internal generation of the PCI clock is insufficient, the AU1500 processor also provides the option to use an externally generated PCI clock. 4.3.1.1 Clock Connections For internal PCI clock generation, the PCI_CLKO pin is used to generate the PCI clock. Note that the generated clock must be fed back into the PCI_CLK pin to drive the PCI interface logic. If an externally generated clock is used, the clock needs to be driven into the PCI_CLK pin, and the PCI_CLKO pin is left unconnected. 4.3.1.2 Limitations on Internal PCI Clock Generation The internal frequency generation circuitry of the AU1500 processor is flexible, but there are limitations on the frequencies that can be generated. Either the CPU PLL or the AUX PLL may be used as the root source of the PCI clock generator. The AUX PLL has the advantage that it is independent of CPU frequency. However, the system designer must take into account that the AUX PLL is also used to generate the USB clocks, which are required to be 48 MHz. All of the frequencies in the system are generated from the 12 MHz oscillator. The AUX PLL multiplies this up to some base frequency, from which the target frequency may be divided. The dividers can be programmed to divide only by even values, which places further constraints on the available frequencies.
AMD AlchemyTM AU1500TM Processor Data Book 81
www..com
30361D PCI 2.2 Bus Controller
If the AUX PLL is to be used to generate both the USB clock and the PCI clock, it should be programmed to 384 MHz by programming the sys_auxpll register to 32. This allows generation of the 48 MHz USB clock by setting the frequency generator to divide by eight. Setting a frequency generator to divide by six can generate a 64 MHz PCI clock, or dividing by twelve can generate a 32 MHz clock. If the AUX PLL is not used for USB clock generation, it can be programmed to 396 MHz and yield 66 MHz and 33 MHz with the same dividers. Alternately, if the CPU is being run at 396 MHz, the CPU PLL can be used as the root clock for a frequency generator with the same effect. 4.3.1.3 Programming Example The CPU PLL and AUX PLL frequencies are programmed by writing to the sys_cpupll and sys_auxpll registers. The value written is multiplied by twelve to yield the resulting PLL frequency. The following configuration example uses the AUX PLL and results in a 64 MHz PCI clock on the PCI_CLKO pin: 1) 2) Write 0x20 to sys_auxpll for an AUX PLL frequency of 384 MHz. Choose a frequency generator for the PCI clock by programming the sys_clksrc register: - Write 0b100 to the MPC field. (For this example frequency generator 2 is used.) - Clear the CPC bit so that the PCI clock is not further divided. 3) Program the sys_freqctrl0 register: - Program the FRDIV2 field to 0x02 so that the frequency is divided by six. - Set the FE2 bit to enable output from frequency generator 2. - Set the FS2 bit to select the AUX PLL as the clock source. For a description of the clock manager registers, see Section 8.1 "Clocks" on page 154.
4.3.2
PCI Interrupts
The PCI_INT[A:D]# signals are only inputs to the AU1500 processor. These signals are routed to the interrupt controller so that the AU1500 can be interrupted on the assertion of these signals. If software needs to generate an interrupt to an external device, a GPIO should be used.
4.3.3
PCI Reset (PCI_RST# and PCI_RSTO#)
The PCI_RST# pin is input only. For systems which require the PCI bus be held in reset as the AU1500 powers up, GPIO[200] (unlike other GPIOs) is configured to output a 0 on power up. System software can use GPIO[200] as a PCI reset output signal (labeled as PCI_RSTO#) to reset the PCI bus without resetting the processor. When the PCI bus is reset, the AU1500 processor PCI configuration registers are also reset. If the state of PCI_RST# is needed by software, another GPIO signal should be used to monitor the status of this pin.
4.3.4
Boot from PCI
The AU1500 has the ability to boot from a memory device on PCI. When the ROMSEL and ROMSIZE pins are both tied high, the AU1500 processor fetches the reset vector from PCI memory space. It is required that the boot memory be located at the AU1500 reset vector physical address because no address translation occurs on master transactions to PCI. The AU1500 processor may not be the clock source or the PCI reset source signal (PCI_RSTO# on GPIO[200]) if booting from PCI, since code is required to configure these functions. Also, the internal arbiter will be used when booting from PCI.
82
AMD AlchemyTM AU1500TM Processor Data Book
www..com
PCI 2.2 Bus Controller 30361D
4.3.5
Host/Satellite Configuration (PCI_CFG)
The PCI_CFG pin determines whether the PCI interface behaves as a host or satellite. If this pin is grounded at reset the PCI interface will be in satellite mode, with configuration registers visible to the PCI bus. If this pin is pulled high at reset the interface will be set to host mode. In host mode the PCI configuration registers are only visible from the internal SBUS and the AU1500 is responsible for configuration of the bus.
4.3.6
PCI Errors
The AU1500 processor error registers (the PCI Configuration/Error register pci_config and the PCI Error Address register pci_err_addr) are intended to be used to supplement the PCI 2.2 Configuration Status bits. PCI error conditions are reflected in the state of pci_config[27:22]. These bits allow software to determine if one or more errors occurred and the cause of at least the first error. Bit 23 (EM) is active only when a second error of any kind shown occurs--that is, when an error is pending while another error occurs. The EM bit allows software to know that multiple errors have occurred since the last time the error conditions were cleared. Once errors are cleared, EM is also cleared so that a subsequent error will be logged as a 'first error'. Table 4-4 shows the possible error conditions reflected in pci_config[27:24].
Table 4-4. PCI Error Conditions on pci_config[27:24]
PCI Mode Target Master PCI Error Condition Parity Error is detected by the AU1500 on a PCI Write to AU1500 memory (and PCI_PERR# is asserted) PCI Master Abort on Configuration Space Read access, due to no response from target device on PCI_DEVSEL# (no device present on selected PCI_IDSEL) PCI Master Abort on Configuration Space Write access, due to no response from target device on PCI_DEVSEL# (no device present on selected PCI_IDSEL) PCI Master Abort on any PCI Read Access, due to transaction not completed in time--address claimed, but PCI_TRDY# or PCI_STOP# not asserted within the number of clocks programmed in pci_timeout[TO]. PCI Master Abort on any PCI Write Access, due to transaction not completed in time--address claimed, but PCI_TRDY# or PCI_STOP# not asserted within the number of clocks programmed in pci_timeout[TO]. PCI Access retried to the same device signaling RETRY more than the number of times programmed in pci_timeout[MR]. PCI Target abort signaled by the addressed Target device AU1500 detects a PCI parity error condition on data received from a target during a read PCI Target signals a PCI parity error condition on PCI_PERR#, from data received from the AU1500 on a PCI Write Transaction Bit 27 ERD 0 1 Bit 26 ET 1 0 Bit 25 EF 0 1 Bit 24 EP 1 0
Master
0
0
1
0
Master
1
0
1
0
Master
0
0
1
0
Master Master Master Master
0 0 1 0
0 0 0 0
1 1 0 0
0 0 1 1
There may be error situations where pci_config and pci_err_addr are not updated when an error occurs. On AU1500 initiated accesses that end in an fatal error, up to two transactions after the error could be discarded because of the asynchronous nature between the PCI bus and the SBUS. However, the address of the transaction to which the fatal error occurred will still be captured.
AMD AlchemyTM AU1500TM Processor Data Book
83
www..com
30361D PCI 2.2 Bus Controller
4.3.7
Readline/ReadMultiple Support
The AU1500 processor will generate Read Line and Read Multiple commands on the PCI bus for AU1500 initiated PCI accesses. If the burst size of the transaction is equal to the cacheline size programmed into the command/status configuration register, then the transaction will be run as a read line transaction on PCI. If the burst size of the transaction is greater than the non-zero cacheline size and a multiple of the non-zero cacheline size, then a read multiple command will be run.
4.3.8
Endian Support
The AU1500 processor PCI block contains support for data swapping and address manipulation to support big endian systems. The Au1 processor core can be set to big endian or little endian. The memory interfaces write according to the byte masks and read the entire 32-bit word. With respect to the AU1500, if the processor is in little endian mode, all accesses are correct since PCI is little endian. For big endian cores there is a choice to be made. The PCI data bus can be connected the same as for little endian or the bytes can be swapped. Table 4-5 shows how the bytes are connected for swapped configurations:
Table 4-5. Data Bus Swapping
SBUS 31:24 23:16 15:8 7:0 PCI 31:24 23:16 15:8 7:0 Swapped PCI 7:0 15:8 23:16 31:24
For memory accesses between the AU1500 processor and external devices, software can choose whether or not to swap the bytes. If one selects to have no swapping, then 32-bit word accesses will read/write values as expected but byte accesses will be big endian from the core and little endian from PCI. For example, if a PCI device has 32-bit control registers and they were accessed with lw/sw from the core, the bit layout would match the devices' specification. But if one of the registers pointed to a buffer in memory that was written/read as a byte stream, the external PCI device would access the data little endian and the processor would access it big endian. Unless the PCI external device has a big endian mode the data would need to be byte swapped by software. The second option would be to swap the data bytes causing the byte accesses to be correct at the cost of word registers needing to be swapped by software. The AU1500 provides the hardware for swapping the data bytes. The endian policy of what to do is left to the system designer based on what accesses are easier to swap, if any. Four control bits are provided to allow system designers to program when and how swapping is done. The four control bits are outlined in Table 4-6:
Table 4-6. Swapping Configurations
pci_config Bits 4 (SM) Function If this bit is set, then for accesses to PCI memory space that are initiated by the Au1 core or DMA devices on the AU1500 SBUS the bytes and byte masks are swapped. If this bit is clear then the bytes are not swapped. If this bit is set, then for accesses to memory from an external PCI master the bytes and byte masks are swapped. If this bit is clear then the bytes are not swapped. For accesses to PCI I/O space initiated by the Au1 core or DMA devices on the AU1500 processor SBUS, the bytes must be swapped or the address changed in big endian mode so that valid PCI I/O accesses can be generated for byte and halfword accesses. The four encodings provide the following actions for both I/O and configuration accesses: 00 The address and byte masks are unchanged. 01 On byte accesses, invert the lower 2 address bits. On halfword accesses, invert the lower address bit. This encoding only affects I/O accesses. 10 On byte and halfword accesses swap the data bytes and leave the address unchanged. 11 Swap the data bytes on all accesses.
84 AMD AlchemyTM AU1500TM Processor Data Book
5 (ST) 7:6 (SIC)
www..com
PCI 2.2 Bus Controller 30361D
Table 4-7 shows the supported modes for the SM, ST and SIC bits based on the endianness of the processor.
Table 4-7. Supported Endian/Swapping Modes
Mode SM ST SIC = 00 SIC = 01 SIC = 10 SIC = 11 Big Endian yes yes no yes (only affects I/O transactions) yes yes Little Endian yes yes yes no no no
4.3.9
PCI Signals
The signals supporting the PCI bus are shown in Table 4-8.
Table 4-8. PCI Bus Support Signals
PCI Signal PCI_AD[31:0] PCI_CBE[3:0]# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PERR# PCI_SERR# PCI_PAR PCI_DEVSEL# PCI_IDSEL PCI_LOCK# PCI_REQ[3:0]# PCI_GNT[3:0]# PCI_INT[A:D]# PCI_CLKO Input/Output I/O I/O I/O I/O I/O I/O I/O O I/O I/O I I/O I O I/O O Definition PCI Address/Data. PCI Bus Command and Byte Enables. PCI Cycle Frame. PCI Initiator Ready. PCI Target Ready. PCI Target Stop. PCI Parity Error. PCI System Error. PCI Parity. PCI Device Select. PCI initialization device select input. PCI Lock for Atomic Operations. PCI Arbiter Bus Request Inputs. PCI Arbiter Bus Grant Outputs. PCI interrupts. PCI Clock Output. Termination Note: Requires an external 22- resistor placed in series within 0.5 inches of the part. PCI_CLK I PCI Input Clock. Termination Note: Should be tied low through a resistor when the PCI bus is not used. PCI_RST# I PCI Reset Input. Termination Note: Should be tied low through a resistor when the PCI bus is not used. PCI_RSTO# (GPIO[200]) O PCI Reset Output. Unlike other GPIOs, GPIO[200] defaults as an output with a zero voltage level coming out of reset. For this reason, GPIO[200] can be controlled by system software to act as a PCI reset output signal (labeled PCI_RSTO#) if needed.
85
AMD AlchemyTM AU1500TM Processor Data Book
www..com
30361D PCI 2.2 Bus Controller
Table 4-8. PCI Bus Support Signals (Continued)
PCI Signal PCI_CFG Input/Output I Definition PCI configuration. Determines the mode (satellite or host) for the PCI interface at hardware reset. For satellite mode, tie PCI_CFG low. For host mode, tie PCI_CFG high. Note that PCI_CFG must not change state after system power up.
4.3.10
Other Notes
The AU1500 PCI contoller cannot be used with external PCI-to-PCI bridges that have PCI bus-mastering devices on the secondary bus which target the AU1500 memory. If the parity enable bit is cleared, the AU1500 will assert PCI_DEVSEL# on target writes in one PCI_CLK. If the parity error enable bit is set, the AU1500 processor will drive PCI_DEVSEL# in two cycles of PCI_CLK on target writes. The AU1500 will not generate or respond to Dual Address Cycles. External PCI masters should not send Dual Address Cycles to the AU1500 processor. The AU1500 processor will not respond to I/O Cycles. External PCI masters should not send I/O cycles to the AU1500 processor. The AU1500 will not respond to Special Cycles. External PCI masters should not send Special cycles to the AU1500 processor. Only Type 0 Configuration cycles are decoded by the AU1500. The AU1500 can generate both Type 0 and Type 1 configuration cycles. The PCI_SERR# signal is only an output. The AU1500 processor will attempt to complete transactions which receive a PCI_SERR#. The Memory Write and Invalidate command is not supported by the AU1500. Setting the Memory Write and Invalidate capable bit in the PCI configuration header has no effect. The AU1500 processor supports PCI cacheline sizes of eight or four 32-bit words.
86
AMD AlchemyTM AU1500TM Processor Data Book
www..com
DMA Controller 30361D
5.0DMA Controller
5
The AU1500 processor contains an eight-channel DMA controller. Each channel is capable of transferring data between memory and any of the integrated peripherals or between memory and a memory-mapped FIFO through the Static Controller using a GPIO as a request. Note that memory-to-memory transfers are not supported by the DMA controller. That is, one side of the DMA transfer must have an incrementing address (memory buffer), while the other side must have a fixed address (FIFO). GPIO[4], GPIO[5], GPIO[208] and GPIO[209] can be programmed to act as external DMA request signals. When configured for this special system function, the pins are labeled as follows: * GPIO[4] becomes DMA_REQ0. * GPIO[5] becomes DMA_REQ1. * GPIO[208] becomes DMA_REQ2. * GPIO[209] becomes DMA_REQ3. See Section 5.2 "Using GPIO as External DMA Requests (DMA_REQn)" on page 92 to configure these GPIO signals to act as DMA requests.
5.1
DMA Configuration Registers
Each channel of the DMA is configured by a register block. A channel register block contains seven registers. The 36-bit physical base address of the register block for each channel is shown in Table 5-1.
Table 5-1. DMA Channel Base Addresses
DMA Channel dma0 dma1 dma2 dma3 dma4 dma5 dma6 dma7 Base Address 0x0 1400 2000 0x0 1400 2100 0x0 1400 2200 0x0 1400 2300 0x0 1400 2400 0x0 1400 2500 0x0 1400 2600 0x0 1400 2700 KSEG1 Base Address 0xB400 2000 0xB400 2100 0xB400 2200 0xB400 2300 0xB400 2400 0xB400 2500 0xB400 2600 0xB400 2700 Priority 0 (highest) 1 2 3 4 5 6 7 (lowest)
AMD AlchemyTM AU1500TM Processor Data Book
87
www..com
30361D DMA Controller
Each register block contains the registers shown in Table 5-2.
Table 5-2. DMA Channel Configuration Registers
Offset 0x0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Register Name dma_moderead dma_modeset dma_modeclr dma_peraddr dma_buf0addr dma_buf0size dma_buf1addr dma_buf1size Description Read channel mode register Set bits in channel mode register Clear bits in channel mode register Address of peripheral FIFO Starting address of buffer 0 Transfer size and remaining transfer count for buffer 0 Starting address of buffer 1 Transfer Size and remaining transfer count for buffer 1
Table 5-3 shows the different peripherals that are capable of DMA. The device ID, transfer size, and transfer width (device FIFO width) are configurable fields in the dma_mode register. The FIFO address is a physical address whose address should be programmed in the dma_peraddr register and in the DAH field of the dma_mode register. Enabling multiple DMA channels with the same device ID is undefined.
Table 5-3. Peripheral Addresses and Selectors
Peripheral Device UART 0 Transmit UART 0 Receive DMA_REQ0 (GPIO[4]) DMA_REQ1 (GPIO[5]) AC97 Transmit AC97 Receive UART3 Transmit UART3 Receive USB Device Endpoint 0 Receive USB Device Endpoint 0 Transmit USB Device Endpoint 1 Transmit USB Device Endpoint 2 Transmit USB Device Endpoint 3 Receive USB Device Endpoint 4 Receive DMA_REQ2 (GPIO[208]) DMA_REQ3 (GPIO[209]) Device ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Transfer Size Programmable Programmable Programmable Programmable 4 4 Programmable Programmable 4 4 4 4 4 4 Programmable Programmable Device FIFO Width 8 8 Programmable Programmable 16 16 8 8 8 8 8 8 8 8 Programmable Programmable FIFO Physical Address 0x0 1110 0004 0x0 1110 0000 Programmable Programmable 0x0 1000 0008 0x0 1000 0008 0x0 1140 0004 0x0 1140 0000 0x0 1020 0000 0x0 1020 0004 0x0 1020 0008 0x0 1020 000C 0x0 1020 0010 0x0 1020 0014 Programmable Programmable
88
AMD AlchemyTM AU1500TM Processor Data Book
www..com
DMA Controller 30361D
5.1.1
DMA Channel Mode Registers
Each DMA channel is controlled by a mode register. The current value of the register can be read from the dma_moderead register but can not be set to an arbitrary value in a single operation. Instead, the configuration register is controlled by two registers: dma_modeset and dma_modeclr. * The dma_modeset register sets bits in the channel mode register when the corresponding bit is written as a one. (Bits written as zero do not affect the corresponding mode bit.) * The dma_modeclr register clears bits in the channel mode register when the corresponding bit is written as a one. (Bits written as zero do not affect the corresponding mode bit.) The AU1500 processor has been designed to simplify the DMA control process by removing the need for a semaphore to control access to the registers. This is because there is no need to read, modify, write, as there are separate registers for setting and clearing a bit. In this way a function can freely manipulate the DMA channels associated with that function. An arbitrary value may be written to a field within the register with the following sequence: dma_modeset = new_value & field_mask; dma_modeclr = ~new_value & field_mask; The Transfer Size and Device Width fields must be programmed to match the FIFO of the peripheral chosen with the DID field according to Table 5-3. For the UART FIFOs the transfer size is programmable. It is the programmers responsibility to insure that the Transfer Size matches the trigger depth set in the UART FIFO control register. See Section 7.5 "UART Interfaces" on page 140 for more information. For external DMA using GPIO signals as requests (DMA_REQn), the system designer must ensure that the Transfer Size and Device Width match the external FIFO and that memory is packed accordingly. Note that before issuing a DMA request, the receiving or transmitting FIFO must be prepared to complete a full transaction (4 or 8 datums, depending on dma_mode[TS]) without risking overflow or underflow.
dma_moderead - Read DMA Mode Register dma_modeset - Set DMA Mode Register dma_modeclr - Clear DMA Mode Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAH DID BE DR TS
9 0
8 0
7 0
6
H
5
G
Offset = 0x0000 Offset = 0x0000 Offset = 0x0004 43210
AB D1 BE1 D0 BE0
DW
NC IE
Def. 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits 31:24 23:20 19:16 15:14 13
Name -- DAH DID -- BE
Description Reserved, should be cleared. Device Address High. Provides the most significant 4 bits of physical device address. Device ID. Identifies the peripheral device to act as source or destination; see Table 5-3 "Peripheral Addresses and Selectors" on page 88. Reserved, should be cleared. Big Endian. 0 1 Little Endian byte order Big Endian byte order
R/W R R/W R/W R R/W
Default 0 0 0 0 0
12
DR
Device Read. 0 1 Data is transferred from memory to device. Data is transferred from device to memory.
R/W
0
11
TS
Transfer Size Number of datums transferred per transaction. The device width is programmed in DW. 0 1 4 datums. (Valid for all device widths.) 8 datums. (Valid for 8-bit and 16-bit device widths only.)
R/W
0
AMD AlchemyTM AU1500TM Processor Data Book
89
www..com
30361D DMA Controller
Bits 10:9
Name DW
Description Device FIFO Width. 00 01 10 11 Transfer width is 8 bits. Transfer width is 16 bits. Transfer width is 32 bits. (Not valid for TS=1.) Reserved
R/W RW
Default 0
8
NC
Not Coherent. 0 1 Memory reads and writes are marked coherent on the SBUS. Memory reads and writes are marked non coherent on the SBUS.
R/W
0
For more information on coherency see Section 2.8.2 "SBUS Coherency Model" on page 42 for more information on coherency. 7 IE Interrupt Enable. 0 1 6 H 0 1 No interrupts will be generated. Interrupts are generated when either D1 or D0 is set. R 0 Channel is active. Channel is halted. R/W 0
Channel Halted.
This bit should be used to determine if the channel has been halted after the G bit has been cleared. 5 G Channel Go. Setting the channel go bit enables the channel. When this bit is cleared the DMA controller does not arbitrate for this channel regardless of the state of the buffer enable bits. When the go bit is cleared by software the channel configuration should not be modified until the DMA controller sets the halt bit to indicate that the channel is inactive and therefore safe to be reconfigured. Active Buffer. 0 1 Buffer 0 is currently in use by the DMA. Buffer 1 is currently in use by the DMA. R/W 0
4
AB
R
0
This field can be read to determine what buffer the DMA will service next if there is not a DMA transaction in progress. During a DMA transaction this bit will reflect the buffer currently being used. Note that the DMA alternates between the two buffers. In other words, it is not possible to only use one buffer, DMA transactions must be switched between each buffer. 3 2 D1 BE1 Done 1. The D1 bit is set by the DMA controller to indicate that a transfer to or from buffer 1 is complete. This bit must be cleared by the processor. The BE1 bit enables buffer 1. This bit is set by the processor and cleared by the DMA controller when the buffer has been filled or emptied. This bit may be cleared by the processor only when the H bit is set. Done 0. The D0 bit is set by the DMA controller to indicate that a transfer to or from buffer 0 is complete. This bit must be cleared by the processor. The BE0 bit enables buffer 0. This bit is set by the processor and cleared by the DMA controller when the buffer has been filled or emptied. This bit may be cleared by the processor only when the H bit is set. R/W R/W 0 0
1 0
D0 BE0
R/W R/W
0 0
90
AMD AlchemyTM AU1500TM Processor Data Book
www..com
DMA Controller 30361D
5.1.2
DMA Peripheral Device Address
The peripheral device address register contains a pointer to the peripheral FIFO to be used as a source or destination. Software is responsible for matching the peripheral address to the correct value of the Device ID (DID) field in the mode register. The correspondence between FIFO address and DID values is shown in Table 5-3 "Peripheral Addresses and Selectors" on page 88. The physical address of the FIFO must be used. The DAH field from the dma_mode register is used as the most significant four bits of the FIFO physical address.
dma_peraddr - DMA Peripheral Address Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0008 3210 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4 0
Bits 31:0
Name ADDR
Description Peripheral FIFO address
R/W R/W
Default 0
5.1.3
DMA Buffer Starting Address Registers
Each DMA channel has two buffers, labeled buffer0 and buffer1. The starting address of each buffer should be written to the dma_buf0addr and dma_buf0addr registers respectively. The starting address must be cache line (32 bytes) aligned. The 4 most significant bits of the buffer address are held in the BAH field of the dma_buf0size and dma_buf1size registers. The starting address must explicitly be written before each DMA transaction, even if the address has not changed from the previous, as dma_bufnaddr will change during the DMA transaction. Note that the DMA alternates between the two buffers. In other words, it is not possible to use only one buffer--DMA transactions must be switched between each buffer. The AB bit in the dma_mode register can be used to determine the active buffer.
dma_buf0addr - Buffer0 Starting Address dma_buf1addr - Buffer1 Starting Address Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000C Offset = 0x0014 43210 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
Bits 31:0
Name ADDR
Description Lower 32 bits of the physical starting address of the DMA memory buffer.
R/W R/W
Default 0
AMD AlchemyTM AU1500TM Processor Data Book
91
www..com
30361D DMA Controller
5.1.4
DMA Channel Buffer Size Registers
The size of each DMA buffer is given by the dma_buf0size and dma_buf1size registers. The buffer size registers also contributes the most significant four bits of the buffer physical address. This register should be programmed with the block size of the buffer in datums. While a DMA transaction is in progress, it indicates the number of datums remaining in the transfer. Note that the DMA alternates between the two buffers. In other words, it is not possible to only use one buffer, DMA transactions must be switched between each buffer. The active-buffer bit dma_mode[AB] can be used to determine which buffer is active at a given time.
dma_buf0size - Buffer 0 Size dma_buf1size - Buffer 1 Size Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BAH Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0010 Offset = 0x0018 43210 0 0 0 0 0
9 0
87 SIZE 00
6 0
5 0
Bits 31:20 19:16 15:0
Name -- BAH SIZE
Description Reserved, should be cleared. Buffer Address High. Provides the 4 most significant bits of the buffer address. Buffer Size and Count Remaining. Indicates the number of datums remaining in the current transfer.
R/W R/W R/W R/W
Default 0 0 0
5.2
1)
Using GPIO as External DMA Requests (DMA_REQn)
For GPIO[4] and GPIO[5]: Write the sys_pininputen to enable the GPIO to be used as an input. See Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168 for more information. For GPIO[208] and GPIO[209]: Be sure that the secondary GPIO block is enabled in gpio2_enable. Also, set the corresponding interrupt-enable bit in gpio2_inten. See Section 7.6 "Secondary General Purpose I/O" on page 149 for more information.
To use GPIO[4], GPIO[5], GPIO[208] or GPIO[209] as an external DMA request (DMA_REQn) follow these steps:
2)
For GPIO[4] and GPIO[5]: TRI-STATE the GPIO to make it an input through the sys_triout register. See Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168 for more information. For GPIO[208] and GPIO[209]: Configure the signals as inputs in gpio2_dir. See Section 7.6 "Secondary General Purpose I/O" on page 149 for more information.
3) 4)
Set the dma_peraddr register to point to the external device data port. The Static Bus Controller must be configured correctly to recognize this address. Program the mode register to match the direction of transfer and peripheral attributes.
The DMA_REQn signal must be driven high to request a DMA transfer and must remain high until the DMA transaction is started. Once started, the DMA transaction continues until finished regardless of the DMA request signal state. A DMA transaction refers to a DMA transfer of one transfer size as defined in the DMA mode register (dma_mode[TS]). DMA_REQn should be tied to the external FIFO threshold indicator. In this way the DMA_REQn signal asserts when the FIFO threshold is reached and remains asserted until the FIFO fills or empties past the threshold (after the DMA transaction starts). DMA_REQn should then negate after the FIFO threshold is met from the opposite direction (approaches full for a transmit or approaches empty for a read). The threshold should be designed such that a complete DMA transaction (4 or 8 datums) can occur without risking overflow or underflow.
92
AMD AlchemyTM AU1500TM Processor Data Book
www..com
DMA Controller 30361D
5.3
Programming Considerations
SetupDMA() { Make sure interrupts are enabled globally (CP0 Reg 12, bit 0) Enable interrupt controller for this DMA channel, high/level Program the DMA controller { dma_modeclr = 0xFFFFFFFF dma_buf0size = buffer size (up to 65535) dma_buf1size = buffer size (up to 65535) dma_peraddr = Address of peripheral FIFO dma_buf0addr = physical base address of buffer dma_buf1addr = physical base address of next buffer Write the dma_modeset register { Enable interrupt Enable both buffers Set endianness Set data width, 8-bit, 16-bit, 32-bit Set Device ID Set transfer size, 4-datum burst, 8-datum burst set coherency = 0 (memory is coherent) set go = 1 } } InterruptHandler() { Note: This routine assumes it is called from context save/ restore routine at 0x80000200. Check for hardware interrupt from interrupt controller 0, request 0: (CP0 Reg 13, bit 10) = 1 Read interrupt controller 0 ic_req0int (interrupt status) and check if source is from this DMA channel, bits[13:6] if it is this DMA channel { Check dma_moderead to see which buffer is done: D0 or D1 if (D0 is set) { write dma_modeclr bit D0 = 1 to clear interrupt if there is another buffer to send { dma_buf0addr = physical base address of buffer dma_buf0size = buffer size (up to 65535) write dma_modeset bit BE0 = 1 to enable buffer } } } if (D1 is set) { write dma_modeclr bit D1 = 1 to clear interrupt if there is another buffer to send { dma_buf1addr = physical base address of buffer dma_buf1size = buffer size (up to 65535) write dma_modeset bit BE1 = 1 to enable buffer } } } } Issue sync }
The following pseudo code is for setting up and servicing a DMA channel:
AMD AlchemyTM AU1500TM Processor Data Book
93
www..com
30361D DMA Controller
94
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Interrupt Controller 30361D
6.0Interrupt Controller
There are two interrupt controllers in the AU1500 processor. Each interrupt controller supports 32 interrupt sources. Interrupts can generate a signal to bring the AU1500 processor out of an IDLE0 or IDLE1 state and generate a CPU interrupt. Each interrupt controller has two outputs referred to as requests 0 and 1. Each of these outputs are connected to the CPU core. See Section 2.5 "Exceptions" on page 27 for a complete AU1500 processor interrupt architecture discussion. Table 61 shows the interrupt controller connections to the CPU.
6
Table 6-1. Interrupt Controller Connections to the CPU
Interrupt Source Interrupt Controller 0: Request 0 Request 1 Interrupt Controller 1: Request 0 Request 1 CP0 Cause Register Bit 10 11 12 13
6.1
Interrupt Controller Sources
Table 6-2 shows the mapping of interrupt sources for Interrupt Controller 0 and 1. Care should be taken to select the correct interrupt type (level or edge triggered) so that an interrupt is not missed. In general, level interrupts are chosen when multiple sources from a single peripheral might cause an interrupt. In this way the programmer will not miss a subsequent interrupt from a particular source while servicing the previous one. Edge triggered interrupts can be used when there is only a single source for an interrupt. Edge triggered interrupts must be used when an interrupt is caused by an internal event and not tied to a register bit where it is latched and held until cleared by the programmer. Details about the interrupt sources can be found in the respective peripheral sections.
Table 6-2. Interrupt Sources
Controller 0 0 0 0 0 0 0 0 0 0 Interrupt Number 0 1 2 3 4 5 6 7 8 9 Source UART0 PCI_INTA# PCI_INTB# UART3 PCI_INTC# PCI_INTD# DMA0 DMA1 DMA2 DMA3 Type High Level Low Level Low Level High Level Low Level Low Level High Level High Level High Level High Level
AMD AlchemyTM AU1500TM Processor Data Book
95
www..com
30361D Interrupt Controller
Table 6-2. Interrupt Sources (Continued)
Controller 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Interrupt Number 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 n = 0..15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Source DMA4 DMA5 DMA6 DMA7 TOY (tick) TOY Match 0 TOY Match 1 TOY Match 2 RTC (tick) RTC Match 0 RTC Match 1 RTC Match 2 PCI Error Interrupt Reserved USB Device Interrupt Request USB Device Suspend Interrupt USB Host AC97 ACSYNC MAC 0 DMA Done MAC 1 DMA Done Reserved AC97 Command Done GPIO[n] GPIO[200] GPIO[201] GPIO[202] GPIO[203] GPIO[20] GPIO[204] GPIO[205] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[206] GPIO[207] Logical OR of GPIO[215:208] (See Section 7.6.2.4 "Interrupt Enable Register" on page 151.) Type High Level High Level High Level High Level Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Internal N/A High Level Rising/Falling edge Low Level Rising Edge High Level High Level N/A Rising Edge System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent System Dependent
96
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Interrupt Controller 30361D
Figure 6-1 shows the Interrupt Controller logic diagram. Where applicable, the names in the diagram correspond to bit n in the relative control register.
ic_rising[n] (rising edge detect) ic_falling[n] (falling edge detect) Edge Detection
ic_req1int[n]
CPU Request 1 32 total
ic_testbit[TB] Interrupt Source Number n
0
1
High Level 32 total
ic_src[n] Low Level (source select) ic_cfg2[n] ic_cfg1[n] ic_cfg0[n] ic_assign[n] Level/Edge Decision Logic ic_mask[n]
CPU Request 0
ic_req0int[n]
Figure 6-1. Interrupt Controller Logic
6.2
Register Definitions
The design of the software interface to the interrupt controller is based on the premise that software tasks should be able to access the value and control of an individual port without blocking other tasks from accessing ports of interest to them. This interrupt controller design removes the need to arbitrate via a semaphore access to the interrupt controller registers. The result is faster and simpler interrupt controller accessing. Table 6-3 shows the base address for each interrupt controller.
Table 6-3. Interrupt Controller Base Addresses
Name ic0_base ic1_base Physical Base Address 0x0 1040 0000 0x0 1180 0000 KSEG1 Base Address 0xB040 0000 0xB180 0000
Each interrupt controller has an identical set of registers that controls its set of 32 interrupts. Table 6-4 shows the interrupt controller registers and their associated offsets. Certain offsets are shared but address different internal registers depending on whether the access is a read or a write. The register description details the functionality of the register. Bit n of a particular register is associated with interrupt n of the corresponding controller.
AMD AlchemyTM AU1500TM Processor Data Book
97
www..com
30361D Interrupt Controller
Table 6-4. Interrupt Controller Registers
Offset (Note 1) 0x0040 0x0040 0x0044 0x0048 0x0048 0x004C 0x0050 0x0050 0x0054 0x0054 Register Name ic_cfg0rd ic_cfg0set ic_cfg0clr ic_cfg1rd ic_cfg1set ic_cfg1clr ic_cfg2rd ic_cfg2set ic_cfg2clr ic_req0int Type R W W R W W R W W R Shows active interrupts on request 0. Used by host software to determine the source of the interrupt. 0x0058 0x0058 0x005C ic_srcrd ic_srcset ic_srcclr R W W Selects the source of the interrupt between a test bit and the designated source. 0 1 0x005C ic_req1int R The test bit (ic_testbit[TB]) is used as interrupt source. Peripheral interrupt (controller 0) or GPIO signal (controller 1) is used for interrupt source. 0x0000 0000 UNPRED 0x0000 0000 Register Description Configuration 0 register Configuration 1 register Configuration 2 register The combined field consisting of ic_cfg2[n], ic_cfg1[n], and ic_cfg0[n] specifies the trigger characteristics for interrupt n as shown in Table 6-5 "Interrupt Configuration Register Function" on page 100. UNPRED Default UNPRED
UNPRED
Shows active interrupts on request 1. Used by host software to determine the source of the interrupt.
0x0060 0x0060 0x0064 0x0068 0x0068 0x006C
ic_assignrd ic_assignset ic_assignclr ic_wakerd ic_wakeset ic_wakeclr
R W W R W W
Assigns the interrupt to one of the CPU requests. 0 1 Assign interrupt to request 1. Assign interrupt to request 0.
UNPRED
Controls whether the interrupt can cause a wakeup from IDLE0 or IDLE1. 0 1 No wakeup from Idle Interrupt will cause wakeup from Idle.
0x0000 0000
The associated interrupt must still be enabled to wake from Idle. 0x0070 0x0070 0x0074 0x0078 0x0078 0x007C 0x007C 0x0080 ic_maskrd ic_maskset ic_maskclr ic_risingrd ic_risingclr ic_fallingrd ic_fallingclr ic_testbit R W W R W R W R/W Interrupt enable. 0 1 Disable the interrupt. Enable the interrupt. UNPRED 0x0000 0000
Designates active rising edge interrupts. If an interrupt is generated off of a rising edge, the associated rising edge detection bit must be cleared after detection. Designates active falling edge interrupts. If an interrupt is generated off of a falling edge, the associated falling edge detection bit must be cleared after detection. This is a single bit register that is mapped to all the source select inputs for testing purposes.
UNPRED
UNPRED
Note 1. See Table 6-3 on page 97 for base address.
98
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Interrupt Controller 30361D
6.2.1
Interrupt Controller Registers
Each register (except the test-bit register) is 32 bits wide with bit n in each register affecting interrupt n in the corresponding controller.
*rd *set *clr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FUNC[31:0] Def. X X X X X X X X X X X X X X X X X X X X X X X
8 X
7 X
6 X
5 X
4 X
3 X
2 X
1 X
0 X
Bits 31:0
Name FUNC[n]
Description The function of each register is given in Table 6-4 "Interrupt Controller Registers" on page 98. FUNC[n] controls the functionality of interrupt n in the corresponding controller.
R/W *rd - read only *set - write only *clr - write only See the following explanation.
Default See Table 6-4 "Interrupt Controller Registers" on page 98.
The test-bit register contains the test bit that can be used as a test source for each interrupt. Figure 6-1 "Interrupt Controller Logic" on page 97 shows how the test bit connects to the interrupt source-select logic.
ic_testbit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0080 3210 TB XXXXX 4
9 X
8 X
7 X
6 X
5 X
Bits 31:1 0
Name -- TB
Description Reserved, should be cleared. Test bit value used as an alternate interrupt source.
R/W R/W R/W
Default UNPRED UNPRED
Certain interrupt controller registers have the same offset but offer different functionality. This is by design. Care should be taken when programming the registers because a read from one location may reference something different from a write to the same location. Registers ending in *rd, *set and *clr have the following functionality: * *rd registers are read only registers will read back the current value of the register. * *set registers are write only registers and will set to 1 all bits that are written 1. Writing a value of 0 will have no impact on the corresponding bit. * *clr registers are write only registers and will clear to zero all bits that are written 1. Writing a value of 0 will have no impact on the corresponding bit.
AMD AlchemyTM AU1500TM Processor Data Book
99
www..com
30361D Interrupt Controller
The three configuration registers have a special functionality in that the value associated with ic_cfg2[n], ic_cfg1[n], ic_cfg0[n] uniquely control interrupt n's functionality as shown in Table 6-5.
Table 6-5. Interrupt Configuration Register Function
ic_cfg2[n] 0 0 0 0 1 1 1 1 ic_cfg1[n] 0 0 1 1 0 0 1 1 ic_cfg0[n] 0 1 0 1 0 1 0 1 Function Interrupts Disabled Rising Edge Enabled Falling Edge Enabled Rising and Falling Edge Enabled Interrupts Disabled High Level Enabled Low Level Enabled Both Levels and Both Edges Enabled
6.3
Hardware Considerations
When using a GPIO or peripheral as an interrupt source, it is important that the associated pin functionality has been enabled in the sys_pinfunc register. In addition when using a GPIO, the GPIO must first be enabled as an input. See Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168 for more information.
6.4
Programming Considerations
The AU1500 has been designed to simplify the interrupt control process by removing the need for a semaphore to control access to the registers. This is because there is no need to read, modify, write, as there are separate registers for setting and clearing a bit. In this way a function can freely manipulate the interrupts associated with that function. If using edge triggered interrupts, it is important to clear the associated edge detection bit or future interrupts will not be seen. Programming an interrupt controller can be broken into the following steps (the set, clr, and rd portion of the register name has been omitted): 1) 2) 3) 4) 5) 6) 7) Identify the interrupt number, n, with the associated peripheral or GPIO. Use ic_src[n] to assign the interrupt to the associated peripheral/GPIO (or the test bit can be used if testing the interrupt). Set the ic_cfg2[n], ic_cfg1[n] and ic_cfg0[n] bits to the correct configuration for the corresponding interrupt (edge, level, polarity). Assign the interrupt to a CPU request using ic_assign[n]. Use ic_wake[n] to assign the interrupt to wake the processor from IDLE if necessary or clear this register bit to keep the interrupt from waking the processor from IDLE. If the interrupt is an edge triggered interrupt, clear the edge detect register (ic_risingclr or ic_fallingclr) before enabling. Finally, enable the interrupt through ic_mask[n].
When taking an interrupt the following steps should be taken: 1) 2) 3) 4) Read ic_req0int and ic_req1int to determine the interrupt number n. Use ic_fallingrd and ic_risingrd to determine if the interrupt was edge triggered. If the interrupt is edge triggered, use ic_fallingclr[n] or ic_risingclr[n] to clear the edge detection circuitry. If the interrupt is to be disabled write ic_maskclr[n]. Service the interrupt.
100
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Peripheral Devices 30361D
7.0Peripheral Devices
This section provides descriptions of the peripheral devices of the AU1500 processor. This includes an AC97 controller, USB Host and Device interfaces, two 10/100 Ethernet MACs and two UARTs.
7
Each peripheral contains an enable register. All other registers within each peripheral's register block should not be accessed until the enable register is written the correct sequence to bring the peripheral out of reset. Accessing the peripheral register block before a peripheral is enabled will result in undefined results.
AMD AlchemyTM AU1500TM Processor Data Book
101
www..com
30361D AC97 Controller
7.1
AC97 Controller
The AU1500 processor contains an AC97 controller which incorporates an AC-link capable of bridging to an AC97 compliant codec.
7.1.1
AC97 Registers
The AC97 controller is controlled by a register block whose physical base address is shown in Table 7-1. The register block consists of 5 registers as shown in Table 7-2.
Table 7-1. AC97 Base Address
Name ac97_base Physical Base Address 0x0 1000 0000 KSEG1 Base Address 0xB000 0000
Table 7-2. AC97 Registers
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x000C 0x0010 Register Name ac97_config ac97_status ac97_data ac97_cmmd ac97_cmmdresp ac97_enable Description AC-link Configuration Controller Status TX/RX Data Codec Command Codec Command Response AC97 Block Control
Note 1. See Table 7-1 for base address.
7.1.1.1 AC-Link Configuration Register The configuration register contains bits necessary to configure and reset the AC-link and codec.
ac97_config - AC-link Configuration Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RC Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0000 3210 SG SN RS 00000 4
9 0
87 XS 00
6 0
5 0
Bits 31:23 22:13
Name -- RC
Description Reserved, should be cleared. Receive Slots. The bits set in RC will control what data from valid slots are put into the input buffer. The corresponding valid bits in the AC97 tag (slot 0 of SDATA_IN) must be marked valid for the incoming PCM data to be put in the input buffer. Slot 3 is mapped to bit 13, slot 4 to 14 and so on. Note: The programmer must ensure that the codec is configured such that there will be valid data in the slots corresponding to what receive slots are enabled.
R/W R R/W
Default 0 0
12:3
XS
Transmit Slots. The bits making up XMIT_SLOTS map to the valid bits in the AC97 tag (slot 0 on SDATA_OUT) and indicate which outgoing slots have valid PCM data. Bit 3 maps to slot 3, bit 4 to slot 4 and so on. Setting the corresponding bit indicates to the codec that valid data will be in the respective slot. The number of valid bits will designate how many words will be pulled out of the FIFO per audio frame. SYNC Gate. Setting this bit to 1 will gate the clock from being driven on SYNC. This allows the SN bit to control the value on SYNC. In combination with SN, the SG bit can be used to initiate a warm reset.
R/W
0
2
SG
R/W
0
102
AMD AlchemyTM AU1500TM Processor Data Book
www..com
AC97 Controller 30361D
Bits 1
Name SN
Description SYNC Control. This bit controls the value of the SYNC signal when SG (SYNC gate) is set. In combination with SG, the SN bit can be used to initiate a warm reset. AC-link Reset (ACRST#) Control. To initiate a cold AC97 reset, set the RS bit to drive the ACRST# signal low. After satisfying the ACRST# low time for the codec, clear this bit to negate ACRST#.
R/W R/W
Default 0
0
RS
R/W
0
7.1.1.2 AC97 Controller Status The AC97 Controller Status register contains status bits for the transmit and receive FIFOs, command status and the codec.
ac97_status - Controller Status Offset = 0x0004 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XU XO RU RO RD CP TE TF RE RF Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
Bits 31:12 11 10 9 8 7
Name -- XU XO RU RO RD
Description These bits are reserved. Transmit Underflow. When set, this bit indicates that the transmit FIFO has experienced an underflow. This sticky bit is cleared when written (0 or 1). Transmit Overflow. When set, this bit indicates that the transmit FIFO has experienced an overflow. This sticky bit is cleared when written (0 or 1). Receive Underflow. When set, this bit indicates that the receive FIFO has experienced an underflow. This sticky bit is cleared when written (0 or 1). Receive Overflow. When set, this bit indicates that the receive FIFO has experienced an overflow. This sticky bit is cleared when written (0 or 1). Ready. This bit is mapped from the CODEC_READY bit in the SDATA_IN tag word. It indicates that the codec is properly booted and ready for normal operation. Command Pending. This bit indicates that there is a command pending on the AC-link. A write to the Codec Command register will cause this bit to be set until the command is completed. The command is completed for a write when the data has been written out on slot 2. The command is completed for a read request when the status data has been read from the corresponding read request. (This means that a read request could be pending for more than 1 cycle depending on the latency of the read.) The command register should not be written until the CP bit is clear. An interrupt can be enabled to indicate when a command is done. The source of this interrupt is an internal pulse so either rising edge or falling edge interrupt should be used for this interrupt.
R/W R R R R R R
Default UNPRED 0 0 0 0 0
6
CP
R
0
5 4 3 2 1 0
-- TE TF -- RE RF
Reserved. Transmit Empty. When set this bit indicates that the transmit FIFO is empty. Transmit Full. When set this bit indicates the transmit FIFO is full. Reserved. Receive Empty. When set this bit indicates that the receive FIFO is empty. Receive Full. When set this bit indicates that the receive FIFO is full.
R R R R R R
UNPRED 0 0 UNPRED 0 0
AMD AlchemyTM AU1500TM Processor Data Book
103
www..com
30361D AC97 Controller
7.1.1.3 TX/RX Data The TX/RX Data register is the transmit FIFO's input to the when written to and the receive FIFO's output when read from. Each FIFO has twelve 16-bit entries. Care should be taken to monitor the status register to insure that there is room for data in the FIFO for a read or write transaction. This will be taken care of automatically if using DMA (see Section 7.1.3 "Programming Considerations" on page 106). The number of bits set in XMIT_SLOTS will correspond with how many samples are pulled out of the FIFO and aligned in the respective slots. The number of bits set in RECV_SLOTS will correspond with the number of samples placed in the FIFO from the respective slots in SDATA_IN.
ac97_data - TX/RX Data Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 DATA_WORD[15:0] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0008 3210 0 0 0 0
4 0
Bits 31:16 15:0
Name -- DATA_WORD
Description Reserved, should be cleared. Data Word. This is where data is written to or read from the FIFO. Each data word is 16 bits.
R/W R R/W
Default 0 0
7.1.1.4 Codec Command The Codec Command and Command Response registers share the same physical address. The Codec Command register is used to send read and write commands to the codec. For write commands, the DATA field will be written to the register indicated by the INDEX field. For read commands, the DATA field should be written zero. The value read from the register indicated by INDEX will appear in the Codec Response register when the Command Pending bit in the status register (ac97_status[CP]) returns to 0. The Codec Command register should only be written if ac97_status[CP] is 0.
ac97_cmmd - Codec Command Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000C 3210 INDEX 00000 4
9 0
76 RW 000
8
5 0
Bits 31:16
Name DATA
Description Data. These bits will be the actual 16-bit word written to the register indicated by INDEX if RW is a 0. If RW is set (indicating a read), these bits should be written 0. Reserved, should be cleared. Read/Write# Bit (1=read, 0=write). This bit maps to the Read/Write# bit in the command address and designates whether the current operation will be a read or a write. Codec Register Index. These bits will address the specific register to be read or written to inside the codec.
R/W W
Default 0
15:8 7
-- RW
W W
0 0
6:0
INDEX
W
0
104
AMD AlchemyTM AU1500TM Processor Data Book
www..com
AC97 Controller 30361D
7.1.1.5 Codec Command Response The Codec Command and Response registers share the same physical address. After a read command is sent through the Codec Command register, the response can be read from the Codec Response register. The command response becomes valid when the Command Pending bit in the status register (ac97_status[CP]) is cleared; however, the response remains valid for only one AC97 frame length in duration (20.8 s).
ac97_cmmdresp - Codec Command Response Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000C 3210 0 0 0 0
9876 READ_DATA 0000
5 0
4 0
Bits 31:16 15:0
Name -- READ_DATA
Description Reserved, should be cleared. Read Data. These bits will be the response to the last read command sent to the codec. The read data becomes valid after the read command is completed (ac97_status[CP] = 0). Note that READ_DATA remains valid for only one AC97 frame (20.8 s) and should therefore be read immediately after ac97_status[CP] is cleared.
R/W R R
Default 0 0
7.1.1.6 AC97 Enable The AC97 Enable register is used to enable and reset the entire AC97 Controller block. The routine for bringing the AC97 controller out of reset is as follows: 1) 2) Set the CE bit to enable clocks while leaving the block disabled (D=1). Clear the D bit to enable the peripheral.
Offset = 0x0010 3210 D CE 00010
ac97_enable - AC97 Block Control Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4
Bits 31:2 1 0
Name -- D CE
Description Reserved, should be cleared. AC97 Controller Disable. Setting this bit will reset the AC97 block. After enabling the clock with CE, this bit should be cleared for normal operation. Clock Enable. This bit should be set to enable the clock driving the AC97 Controller. It can be cleared to disable the clock for power considerations.
R/W W W W
Default 0 1 0
AMD AlchemyTM AU1500TM Processor Data Book
105
www..com
30361D AC97 Controller
7.1.2
Hardware Considerations
The AC-link consists of the signals listed in Table 7-3.
Table 7-3. AC-Link Signals
Signal ACSYNC ACBCLK ACDO ACDI ACRST# Input/Output O I O I O Definition Fixed Rate Sample Sync. Serial Data Clock. TDM Output Stream. TDM Input Stream. Codec Reset.
For changing pin functionality please refer to the sys_pinfunc register in Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168.
7.1.3
Programming Considerations
The AC97 block supports DMA transfers and interrupts. The use of the DMA or interrupts is program dependent and is not required to use the AC97 controller. To use DMA for AC97 memory transfers the transmit and receive functions will each need a dedicated DMA channel. The DMA peripheral address register (dma_peraddr) in the DMA configuration registers will be set to point to the AC97 ac97_data register. The DMA mode register (dma_mode) will need to be set up with the correct Device ID (DID). The Device Read bit (DR) will depend on whether the channel is being used for receive or transmit. Typically the Device Width (DW) should be set to 16 bits and the transfer size bit (TS) should be cleared because the FIFO threshold indicators correspond to four-datum transfers. This assumes that the audio samples are aligned in memory on a 16-bit audio sample boundary. The DMA will automatically monitor the transmit and receive request bits and feed data accordingly. An interrupt ("AC97 Command Done" in interrupt controller 0) can be enabled to indicate when a command is completed. The source of this interrupt is an internal pulse so either rising edge or falling edge interrupt should be used for this interrupt. When the AC97 ACSYNC interrupt is enabled in interrupt controller 0, an interrupt will occur corresponding to the rising edge of the ACSYNC signal. Internally a pulse is generated from the rising edge of the ACSYNC signal and fed to the interrupt controller. Regardless of the edge enabled in the interrupt controller the interrupt will come after the rising edge of ACSYNC. Enabling a rising edge interrupt will interrupt the processor closest to the rising edge of ACSYNC. The output FIFO for the AC-link is shared for all slots so care should be taken that there is a correspondence with the number of valid bits being set and the number of valid samples written to the transmit FIFO or aligned in memory for DMA or erroneous results will occur. It is the programmer's responsibility to ensure that the number of samples written to the FIFO corresponds with the number of valid slots enabled. Data will automatically be pulled out of the FIFO in the order of what slots are enabled. In other words if slots 3, 4, 6 and 9 are enabled, the programmer should write samples corresponding to data for slots 3, 4, 6, and 9, in that order, to the FIFO. To insure against underflow at least x words should be written per audio frame where x is the number of slots enabled. This is a mean rate over time and the actual write rate may differ depending on latency requirements, DMA buffer size, and the number of slots enabled. Care should be taken that there is a correspondence with the number of valid bits that have been set and the number of valid samples read from the receive FIFO or erroneous results will occur. The input FIFO for the AC-link is shared for all slots so care should be taken that there is a correspondence with the number of valid bits that are set and the number of samples read from the receive FIFO or erroneous results will occur. It is the programmer's responsibility to ensure that the number of samples read from the FIFO corresponds with the number of valid slots enabled. Data will automatically be put in the FIFO in the order of what slots are enabled. In other words if slots 3 and 4, are enabled, the programmer should read samples corresponding to data for slots 3 and 4, in that order, from the FIFO. To insure against overflow at least x words should be read per audio frame where x is the number of slots enabled. This is a mean rate over time and the actual read rate may differ depending on latency requirements, DMA buffer size, and the number of slots enabled.
106
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Host Controller 30361D
7.2
USB Host Controller
The AU1500 processor USB host controller conforms to the Open HCI interface specification, revision 1.0, and is USB 1.1 compliant. Two root hub ports, port 0 and port 1, are provided. The base of the Open HCI register block is shown in Table 74.
Table 7-4. USB Host Base Address
Name usbh_base Physical Base Address 0x0 1010 0000 KSEG1 Base Address 0xB010 0000
Only 32-bit accesses are allowed to the Open HCI registers. All interrupts as described in the Open HCI specification are supported. These interrupts are combined when brought to the interrupt controller into one active-low interrupt (negative-edge triggered does not work). The interrupt controller should be programmed to reflect this by setting the USB Host interrupt to low level. See Section 6.0 "Interrupt Controller" on page 95 for details.
7.2.1
USB Host Enable Register
This register is not part of the OpenHCI registers; however, it shares the same base address. The usbh_enable register controls the reset and clocks to the USB Host controller. When initializing the USB Host controller the programmer should first enable clocks, then enable the module (remove from reset), then wait for the RD bit to be set before performing OpenHCI initialization. The correct routine for bringing the USB Host Controller out of reset is as follows: 1) 2) 3) 4) Set the CE bit to enable clocks. Set the E bit to enable the peripheral (at this time the C and BE bits should be configured appropriately for the system). Clear the HCFS bit in the HcControl register to reset the OHCI state. Wait for the RD bit to be set before issuing any commands to the OpenHCI controller.
To put the USB Host Controller into reset the following steps should be taken: 1) 2) Set the HCFS bit in the HcControl register. Clear the E and CE bits.
Offset = 0x7FFFC 43210 RD CE E C BE 000000 5
usbh_enable Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
Bits 31:5 4
Name -- RD
Description Reserved, must be cleared. Reset Done. Wait for this bit to be set before issuing any commands to the OpenHCI controller. Note: When writing to the usbh_enable register, this bit position must be 0.
R/W R/W R
Default 0 0
3 2 1
CE E C
Clock Enable. When this bit is set, clocks are enabled to the USB Host controller. Enable. This bit enables the USB Host controller. When this bit is clear the controller is held in reset. Coherent. If this bit is set memory accesses by the controller will be marked coherent on the SBUS. When this bit is clear memory accesses by the USB Host controller are non coherent. For more information on coherency see Section 2.8.2 "SBUS Coherency Model" on page 42 for more information on coherency.
R/W R/W R/W
0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
107
www..com
30361D USB Host Controller
Bits 0
Name BE
Description Big Endian. When this bit is set the controller interprets data buffers in Big Endian byte order. When this bit is clear the controller interprets data buffers in Little Endian byte order. Setting the BE bit does not swap the control structures defined in the OHCI specification. Endpoint descriptors (section 4.2), transfer descriptors (section 4.3), and the HCCA (host controller communications area, section 4.4) should always be written as words to ensure proper operation.
R/W R/W
Default 0
7.2.2
USB Host Signals
Table 7-5 shows the signals associated with the two USB host root hub ports. The USB root hub port pins have USB 1.1 compliant drivers with the addition of the external circuitry noted in the signal description.
Table 7-5. USB Host Signals
Signal USBH0P Input/Output I/O Description Positive signal of differential USB host port 0 driver Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27- resistor placed in series within 0.5 inches of the part. Muxed with USBDP which controls the pin out of reset. USBH0M I/O Negative signal of differential USB host port 0 driver Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27 ohm resistor placed in series within 0.5 inches of the part. Muxed with USBDM which controls the pin out of reset. USBH1P I/O Positive signal of differential USB host port 1 driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27 ohm resistor placed in series within 0.5 inches of the part. USBH1M I/O Negative signal of differential USB host port 1 driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27 ohm resistor placed in series within 0.5 inches of the part.
For changing pin functionality please refer to the sys_pinfunc register in Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168.
108
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Device Controller 30361D
7.3
USB Device Controller
The AU1500 processor USB device controller supports endpoints 0, 1, 2, 3, and 4. Endpoint 0 is always configured as a bidirectional control endpoint. Endpoints 1 and 2 are always IN endpoints and endpoints 3 and 4 are always OUT endpoints. IN is from device to host. From the device perspective these endpoints are written, so the associated registers are tagged with write or wr. OUT is from host to device. From the device perspective these endpoints are read, so the associated registers are tagged with read or rd.
7.3.1
USB Device Controller Registers
The USB device registers are located off of the base address shown in Table 7-6. Table 7-7 shows the offsets of each register from the register base
Table 7-6. USB Device Base Address
Name usbd_base Physical Base Address 0x0 1020 0000 KSEG1 Base Address 0xB020 0000
Table 7-7. USB Device Register Block
Offset (Note 1) 0x0000 0x0004 0x0008 0x000c 0x0010 0x0014 0x0018 0x001c 0x0020 0x0024 0x0028 0x002c 0x0030 0x0034 0x0038 0x0040 0x0044 0x0048 0x004c 0x0050 0x0054 0x0058 Name usbd_ep0rd usbd_ep0wr usbd_ep1wr usbd_ep2wr usbd_ep3rd usbd_ep4rd usbd_inten usbd_intstat usbd_config usbd_ep0cs usbd_ep1cs usbd_ep2cs usbd_ep3cs usbd_ep4cs usbd_framenum usbd_ep0rdstat usbd_ep0wrstat usbd_ep1wrstat usbd_ep2wrstat usbd_ep3rdstat usbd_ep4rdstat usbd_enable Function Read from endpoint 0 Write to endpoint 0 Write to endpoint 1 Write to endpoint 2 Read from endpoint 3 Read from endpoint 4 Interrupt Enable Register Interrupt Status Register Write Configuration Data Endpoint 0 control and status Endpoint 1 control and status Endpoint 2 control and status Endpoint 3 control and status Endpoint 4 control and status Current frame number EP0 Read FIFO Status EP0 Write FIFO Status EP1 Write FIFO Status EP2 Write FIFO Status EP3 Read FIFO Status EP4 Read FIFO Status USB Device Controller Enable
Note 1. See Table 7-6 for base address.
AMD AlchemyTM AU1500TM Processor Data Book
109
www..com
30361D USB Device Controller
7.3.1.1 Endpoint FIFO Read and Write Registers The endpoint FIFO read and write registers provide access to the endpoint FIFOs. Each endpoint FIFO is unidirectional. FIFO read registers may not be written, and FIFO write registers return unpredictable results if read. Only the least significant byte of the FIFO registers contain data.
usbd_ep0rd usbd_ep0wr usbd_ep1wr usbd_ep2wr usbd_ep3rd usbd_ep4rd Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0000 Offset = 0x0004 Offset = 0x0008 Offset = 0x000C Offset = 0x0010 Offset = 0x0014 43210 DATA 00000
9 0
8 0
7 0
6 0
5 0
Bits 31:8 7:0
Name -- DATA
Description Reserved, should be cleared. Data. Byte of data to be written to, or read from the endpoint FIFO.
R/W R/W R/W
Default 0 0
7.3.1.2 Interrupt Registers Each endpoint has an interrupt enable register and an interrupt status register. The two registers have identical formats. When a condition becomes true the corresponding bit is set in the usbd_intstat register. If a bit is set in the interrupt enable register and the corresponding condition becomes true, then an interrupt is issued. The interrupt for the USB device should be programmed to high level. Interrupts and pending conditions must be cleared by writing a 1 to the corresponding bit in the usbd_intstat register.
usbd_inten Offset = 0x0018 usbd_intstat Offset = 0x001C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SF H5 H4 H3 H2 H1 H0 C5 C4 C3 C2 C1 C0 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 31:13 12 11:6
Name -- SF H5:H0
Description Reserved, should be cleared. Start of Frame. This interrupt issues when an SOF token is received. FIFO Half Full. These interrupts issue when the corresponding FIFO reaches the half full/half empty mark. The bits correspond as follows: H0 - ep0rd H1 - ep0wr H2 - ep1wr H3 - ep2wr H4 - ep3rd H5 - ep4rd
R/W R/W R/W R/W
Default 0 0 0
5:0
C5:C0
Complete. These interrupts issue when a transmission or reception completes on the corresponding FIFO. For the read FIFOs (ep0rd, ep3rd, and ep4rd) these interrupts indicate the reception of a DATA0 or DATA1 packet, or a SETUP packet (ep0rd FIFO only). For the write FIFOs (ep0wr, ep1wr, and ep2wr) these interrupts indicate the transmission of a DATA0 or DATA1 packet. The bits correspond as follows: C0 - ep0rd C1 - ep0wr C2 - ep1wr C3 - ep2wr C4 - ep3rd C5 - ep4rd
R/W
0
110
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Device Controller 30361D
7.3.1.3 Device Configuration Register The device configuration register allows configuration data to be loaded to the controller after reset.
usbd_config Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0020 43210 CFGDATA 000000 5
9 0
8 0
7 0
6 0
Bits 31:8 7:0
Name -- CFGDATA
Description Reserved, should be cleared. Configuration data byte. Use this field to write the configuration data block to the controller one byte at a time.
R/W R/W R/W
Default 0 0
The device configuration data is a 25-byte block which contains the configuration information for the five supported endpoints. Each endpoint requires five configuration bytes in the format shown in Figure 7-1.
Bit: Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 0 0 0 0 0 7 6 5 4 3 0 Direction 2 1 1 0 0 0
Endpoint number 0 Type
Max packet size[9:7] 0 0 0 0
Max packet size[6:0] 0 0 0 0 0
FIFO number
Figure 7-1. Endpoint Configuration Data Structure
The configuration fields are described in Table 7-8.
Table 7-8. Endpoint Configuration Field Descriptions
Field Endpoint Number Type Description Although the endpoint number ranges from 0 to 15, only endpoints 0, 1, 2, 3, and 4 are supported. It is highly recommended that the example values in Table 7-9 on page 112 be used for this field. Endpoint type. 00 01 10 11 Direction Control Isochronous Bulk Interrupt
Endpoint direction. (Does not apply to control endpoints.) 0 1 Out In
Max Packet Size
Maximum packet size (in bytes). Note that for control, bulk, and interrupt endpoints, the maximum packet size is limited to 64 bytes. Only isochronous endpoints can accept packets up to 1023 bytes. 000 0000 000 000 0000 001 ... 111 1111 111 = 0 bytes = 1 byte = 1023 bytes
FIFO Number
This field designates which FIFO the endpoint uses. For endpoint 0 this field is ignored since endpoint 0 always uses FIFOs 0 and 1. It is highly recommended that the example values in Table 7-9 on page 112 be used for this field.
AMD AlchemyTM AU1500TM Processor Data Book
111
www..com
30361D USB Device Controller
After the controller is removed from reset, the device configuration data must be written to the usbd_config register in order beginning with byte 0. Bytes are written individually using unsigned 32-bit words, as shown the following example code: for (i=0; i<25; i++) *usbd_config = (unsigned int) cfg_data_bytes[i]; An example configuration data block is shown in Table 7-9.
Table 7-9. Example Endpoint Configuration Data Block
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Value 0000 0100 0000 0000 1000 0000 0000 0000 0000 0000 0001 0100 0011 1000 1000 0000 0000 0000 0000 0010 0010 0100 0010 1000 1000 0000 0000 0000 0000 0011 0011 0100 0010 0000 1000 0000 0000 0000 0000 0100 0100 0100 0010 0000 1000 0000 0000 0000 0000 0101 Description Endpoint number = 0 Type = control Direction = bidirectional Max packet size = 64 bytes FIFOs 0 and 1 Endpoint number = 1 Type = interrupt Direction = in Max packet size = 64 bytes FIFO 2 Endpoint number = 2 Type = bulk Direction = in Max packet size = 64 bytes FIFO 3 Endpoint number = 3 Type = bulk Direction = out Max packet size = 64 bytes FIFO 4 Endpoint number = 4 Type = bulk Direction = out Max packet size = 64 bytes FIFO 5
112
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Device Controller 30361D
7.3.1.4 Endpoint Control Registers The endpoint control registers define parameters and reflect operational conditions for each endpoint.
usbd_ep0cs Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SU N A B Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usbd_ep1cs usbd_ep2cs Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SU N A Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usbd_ep3cs usbd_ep4cs Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SU N A Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0024 3210 FS 00000 4 Offset = 0x0028 Offset = 0x002C 43210 FS 00000 Offset = 0x0030 Offset = 0x0034 43210 FS 00000
9 0
8 0
7 0
6 SZ 0
5 0
9 0
8 0
7 0
6 SZ 0
5 0
9 0
8 0
7 0
6 0
5 0
Bits 31:15 14 13
Name -- SU N
Description Reserved, should be cleared. Setup Received - This bit is set when a SETUP packet is received from the host. It is only valid for EP 0. NAK. This bit is set when an operation does not complete successfully or when data in a receive FIFO should be ignored. For most cases this implies a returned NAK in response to a DATA packet or an incorrect CRC. ACK. This bit is set when an operation completes successfully. Most of the time this means that the Host returned an ACK to a DATA (or SETUP) packet or that a packet was received correctly and an ACK returned to the Host. Isochronous DATA and SETUP packets deviate from this model. For these types of packets the A bit indicates successful transmission or reception but no ACK is returned or expected.
R/W R/W R R
Default 0 0 0
12
A
R
0
11 10:1 0
B SZ FS
Alternate ACK - Set when a DATA frame is correctly received on endpoint 0. (B is not present on other endpoints.) The SZ field specifies the data size of an IN transfer. The SZ field applies only to endpoints 0, 1, and 2. Force Stall. Setting this bit places the endpoint in a stalled condition. Any transaction directed to the endpoint is answered with a STALL response. STALL is typically used to indicate that the endpoint has halted. Note that a Clear Feature command received via the USB does not clear a stall condition forced by this bit.
R R/W R/W
0 0 0
7.3.1.5 Current Frame Number This register provides the current frame number from the start of frame packet.
usbd_framenum - Current Frame Number Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0038 3210 0 0 0 0
9 0
8 0
7 0
54 FN 000
6
Bits 31:11 10:0
Name -- FN
Description Reserved, should be cleared. Frame Number. This field contains the frame number from the start of frame packet.
R/W R R
Default 0 0
AMD AlchemyTM AU1500TM Processor Data Book
113
www..com
30361D USB Device Controller
7.3.1.6 FIFO Status Registers Each FIFO has a status register that indicates the current state and any error conditions. The USB FIFOs are 1-byte wide and eight bytes deep.
usbd_ep0rdstat usbd_ep0wrstat usbd_ep1wrstat usbd_ep2wrstat usbd_ep3rdstat usbd_ep4rdstat Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0040 Offset = 0x0044 Offset = 0x0048 Offset = 0x004C Offset = 0x0050 Offset = 0x0054 76543210 FL UF OF FCNT 00000000
9 0
8 0
Bits 31:7 6 5 4 3:0
Name -- FL UF OF FCNT
Description Reserved, should be cleared. Flush FIFO. Setting this bit flushes the corresponding FIFO and discards any data contained in it. Underflow Flag. Set when attempting a read from an empty FIFO. Clear this flag by writing a 1 to it. Overflow Flag. Set if a byte is written to a full FIFO. Clear this flag by writing a 1 to it. FIFO Count. Reflects the current number of bytes (0 to 8) in the corresponding FIFO.
R/W R/W W R/W R/W R
Default 0 0 0 0
7.3.1.7 Device Controller Enable Register The USB device controller enable register (usbd_enable) controls the clocks and reset to the device controller. The programmer should first enable clocks before enabling the device controller. To bring the USB device out of reset, follow these steps: 1) 2) 3) 4) Set the CE bit to enable clocks. Delay for a period greater than or equal to 1 s. Set the E bit to enable the peripheral. Delay at least 1 s before programming any registers in the peripheral.
Offset = 0x0058 3210 SI CE E 00000
usbd_enable Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4
Bits 31:3 2
Name -- SI
Description Reserved, should be cleared. Streaming Isochronous Mode. Clearing this bit allows isochronous endpoints to service IN and OUT transactions when the endpoint interrupt is pending. This mode is enabled by default. Setting this bit (not recommended) forces ISO endpoints to wait for pending interrupts to be cleared before accepting further data.
R/W W W
Default 0 0
1 0
CE E
Clock Enable. Clearing this bit disables all clocks to the USB Device core. Setting this bit allows normal operation. Enable. When this bit is cleared the Device Controller will be held in reset. Setting this bit enables normal operation.
W W
0 0
114
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Device Controller 30361D
7.3.2
Programming Considerations
7.3.2.1 Removing the Controller from Reset The following sequence of operations must be applied to remove the controller from reset. 1) 2) 3) 4) 5) Write a 0x0002 to the usbd_enable register to enable the clocks. Wait 1 s. Write a 0x0003 to the usbd_enable register to remove the controller from reset. Wait 1s. Write 25 bytes of configuration data to the usbd_config register.
There are no special constraints on entering the reset state: One write to the usbd_enable register may be used to turn the clocks off and reset the controller. Note: Accessing the endpoint control registers (usbd_epncs), frame number register (usbd_framenum) or configuration data register (usbd_config) while the USB device is in suspend mode will result in a System Bus (SBUS) deadlock. This will inhibit any further operation of the CPU, including EJTAG debugger operation. 7.3.2.2 Latency Requirements The time from reception of a token such as IN or OUT until the controller must source the corresponding DATA frame is very short. It is not practical to wait for a token before preparing the buffer for the response. Buffers must be posted before the token is received. The token itself is not passed to the buffer--only DATA and SETUP frames are transferred. When a DATA or SETUP frame is received the difference between an OUT and a SETUP can be determined by examining the SU bit in the usbd_ep0cs register. (Only endpoint 0 should receive SETUP packets.) If an IN endpoint is enabled and no data is available in the FIFO the endpoint will NAK. Underrunning the FIFO during a transfer (after the first byte has been written to the FIFO) will result in a bit stuff error. 7.3.2.3 Using DMA DMA should be used for all transfers with the exception of the FIFO cleanout described below for OUT transactions. For IN transactions the size in the usbd_epncs register should be set to MAXPACKET for all but the last buffer and to the actual remaining transfer size for the last packet. The DMA size must be set to match usbd_epncs before the DMA is enabled for proper frame transmission. If the last buffer of an IN series is a full MAXPACKET in length it may be necessary to set the size in the usbd_epncs register to zero and write a byte to the FIFO to enable the transmission of a zero length DATA frame since this is often the indicator for end-of-transfer. In this case the FIFO must be cleared before the next buffer is set up. For OUT endpoints the DMA may be programmed to a larger size than a transfer will use. When the endpoint completes the FIFO should be examined to see if there are any remaining bytes available. These bytes must be read from the FIFO under program control since the DMA will not receive a request when less than 4 bytes are in the FIFO. For endpoint zero it is necessary to keep a DMA buffer enabled at all times since SETUP and OUT transactions can come at any time. The user should implement a circular buffer and extract transactions from this buffer in software, rather than trying to have the DMA place transactions into separate buffers. 7.3.2.4 Servicing Interrupts When an interrupt is received the usbd_intstat register should be read to determine the cause of the interrupt. Once the interrupt has been serviced the usbd_intstat register should be written with the same value to clear the interrupt. When an IN or OUT transaction is completed the device controller will NAK all further IN/OUT tokens until the interrupt is cleared by writing the usbd_intstat register. This allows the interrupt service routine time to drain the FIFO and set up for the next transaction rather than concatenating data from separate transactions. This automatic wait can be disabled for isochronous endpoints by clearing usbd_enable[SI]. SETUP packets can never be delayed with NAK. For bulk, isochronous, and interrupt endpoints the A and N flags are somewhat redundant. Only one of them should be set for a given transaction.
AMD AlchemyTM AU1500TM Processor Data Book
115
www..com
30361D USB Device Controller
For the control endpoint the flags are broken out to provide separate feedback for various phases of control transactions. This is necessary since only the IN and OUT phases can be paused with NAKs. SETUP packets must be absorbed gracefully at all times. The A flag (ACK) is set to indicate successful reception of OUT or SETUP packets. The B flag (alternate ACK) is set to indicate successful reception of OUT data only. (SETUP packets do not affect this flag.) The N flag (NAK) is set to indicate an unsuccessful attempt to send data in response to an IN token. This combination of flags allows all situations to be decoded. The most complex of these is when a SETUP packet immediately follows an OUT phase used to acknowledge the previous transaction. Without this separation the acknowledgement would be lost. 7.3.2.5 Automatic Execution of Commands Some standard setup commands directed at endpoint zero are automatically serviced by the USB device hardware. These commands are still passed to the memory buffer. No further action is required to service these commands although they may be used to signal state changes within the software. The following commands are automatically serviced: * Set Address * Set/Clear Feature * Set/Get Configuration * Set/Get Interface * Get Status 7.3.2.6 Detecting USB Reset The USB device controller does not provide a way to detect reset on the USB. It is recommended that if a device needs to change state on reset it should use the reception of a Set Address command to indicate that a reset has occurred. 7.3.2.7 Automatic Suspension If the USB device is Idle for more than 5 ms, the device controller enters a suspend state. In this state the device controller does not consume data. A rising edge suspend interrupt is provided to inform the CPU when this occurs. The suspend interrupt may also be used to detect the exit from suspend by using the falling edge of the interrupt. Note: Because the USB device controller will suspend itself if left Idle, the USB device configuration routine (including programming the interrupt controller to recognize request and suspend interrupts from the USB device) must be fully completed within 5 ms of bringing the peripheral out of its reset state. 7.3.2.8 Re-establishing a Connection after Reset During software initialization of the USB device controller, the USBDP and USBDM signals do not automatically enter a disconnect-bus state in which both signals go low for more than 2.5 s. Instead, after a runtime or hardware reset of the system, the signals stay in a connect-bus state in which USBDP remains high and USBDM remains low. This prevents the USB host from recognizing the need to establish a new bus enumeration, and the logical communication flow remains disrupted. To re-establish logical communication after reset, system initialization software can control a GPIO signal to temporarily (more than 2.5 s) disable power to USBDP. It is recommended to use the GPIO to toggle an LDO (low drop-out) voltage regulator placed between the USB power supply (VBUS) and the pull-up resistor attached to USBDP.
116
AMD AlchemyTM AU1500TM Processor Data Book
www..com
USB Device Controller 30361D
7.3.3
Programming Examples for USB Device
7.3.3.1 Initialization 1) Configure 4 8MHz USB device clock from AUX PLL. sys_auxpll = 16; // set the AUX PLL to 192 MHz (12 MHz x 16) sys_freqctrl0 |= 0x3; // enable FREQ0 and select AUX PLL as the FREQ0 source sys_clksrc |= 0xB; // divide FREQ0 by 4 to obtain 48 MHz, and select FREQ0 as the USB clock 2) Enable USB Device Controller. usbd_enable = wait at least usbd_enable = wait at least 3) 0x02; 1us; 0x03; 1us; // enable USBD clocks // remove reset from USBD Controller
Write 25-byte configuration data to the Configuration Register. for( i = 0; i < 25; ++i ) { usbd_config = (unsigned int) config_data_bytes[i]; } wait at least 1us;
4)
Set up Endpoint Control Registers (example). usbd_ep0cs usbd_ep1cs usbd_ep2cs usbd_ep3cs usbd_ep4cs = = = = = 64 << 1; 8 << 1; 8 << 1; 8 << 1; 8 << 1; // // // // // set set set set set endpoint endpoint endpoint endpoint endpoint 0 1 2 3 4 MAXPACKET MAXPACKET MAXPACKET MAXPACKET MAXPACKET
5)
Clear FIFO Status Registers. // clear Overflow Flag, Underflow Flag, Flush FIFO usbd_ep0rdstat = 0x70; usbd_ep0wrstat = 0x70; usbd_ep1wrstat = 0x70; usbd_ep2wrstat = 0x70; usbd_ep3rdstat = 0x70; usbd_ep4rdstat = 0x70;
6)
Configure DMA channels. // assign a multiple // assign a multiple // assign a multiple // assign a multiple // assign a multiple // assign a multiple DMA channel for endpoint 0 receive and build buffer descriptors DMA channel for endpoint 0 transmit and build buffer descriptors DMA channel for endpoint 1 transmit and build buffer descriptors, if necessary DMA channel for endpoint 2 transmit and build buffer descriptors, if necessary DMA channel for endpoint 3 receive and build buffer descriptors, if necessary DMA channel for endpoint 4 receive and build buffer descriptors, if necessary
7) 8) 9)
Configure the interrupt type for the USB device request (interrupt controller 0, number 24) as high-level. Configure the interrupt type for the USB device suspend (interrupt controller 0, number 25) as rising-edge. Start the Endpoint 0 receive DMA.
10) Enable USB Interrupts. usbd_inten = 0x0000003f;// enable transfer-complete interrupts
AMD AlchemyTM AU1500TM Processor Data Book 117
www..com
30361D USB Device Controller
7.3.3.2 Interrupt Handler The steps to handle an interrupt are shown below. This example handler is for a general USB application and may not be sufficient for a specific application. The handler must be installed before interrupts are enabled. 1) Obtain the USBD interrupt status. status = usbd_intstat// obtain usbd_intstat 2) Execute each interrupt condition. // check { // if // if // if // if // if // if } 3) if endpoint transfer complete ep0rd ep0wr ep1wr ep2wr ep3rd ep4rd completed, completed, completed, completed, completed, completed, execute execute execute execute execute execute the the the the the the process process process process process process for for for for for for ep0rd. ep0wr. ep1wr. ep2wr. ep3rd. ep4rd.
Clear the USBD interrupt status. usbd_intstat = status;// clear interrupts
7.3.4
Hardware Considerations
Table 7-10 shows the signals associated with the USB device. The USB root hub port pins have USB 1.1 compliant drivers with the addition of the external circuitry noted in the signal description. The USB device implementation is full speed with the required termination noted in Table 7-10. Low speed is not supported.
Table 7-10. USB Device Signals
Signal USBDP Input/Output I/O Description Positive signal of differential USB device driver. Requires a 1.5 kohm pull-up resistor to denote a full speed device. Also requires an external ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27 ohm resistor placed in series within 0.5 inches of the part. Muxed with USBH0P USBDM I/O Negative signal of differential USB device driver. Requires an external ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Termination Note: Requires an external 27 ohm resistor placed in series within 0.5 inches of the part. Muxed with USBH0M
For changing pin functionality please refer to the sys_pinfunc register in Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168.
118
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
7.4
Ethernet MAC Controller
The AU1500 processor contains two Ethernet MAC devices. The MAC provides the interface between the host application and the PHY layer through the Media Independent Interface (MII). The PHY layer device is external to the processor. The MAC supports the protocol requirements to meet the Ethernet/IEEE 802.3 specification. The MAC operates in both half and full duplex modes. In half duplex mode the MAC is compliant with section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard) and ANSI/IEEE 802.3. The MAC provides programmable enhanced features designed to minimize host supervision, bus utilization and pre/post message processing. These features include ability to disable retries after a collision, dynamic FCS generation on a frame by frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmission and detection of collision frames. The MAC can sustain transmission or reception of minimal size back-to-back packets at full line speed with an inter-packet gap of 9.6 s for 10 Mbps and 0.96 s for 100 Mbps. A dedicated DMA engine is implemented to support the MAC so that the general purpose DMA is not required. The primary attributes of the MAC are: * Transmit and receive message data encapsulation with framing and error detection. * Frame boundaries are delimited and frames are synchronized. Error detection is done at the physical medium transmission level. * Media access management is supported through medium allocation and contention resolution. This is accomplished through collision avoidance and handling. The MAC handles collision per the ISO 8802.3 specification. * Support for flow control during full duplex mode is accomplished by decoding of control frames and disabling the transmitter in conjunction with generation of control frames. * The serial control interface supports the MII protocol to interface to an MII based PHY. The MAC features are: * IEEE 802.3, 802.3u, 803.3x specification compliance * 10/100 Mbps data transfer rates * IEEE 802.3 compliant MII interface to talk to an external PHY * Full and half duplex * CSMA/CD in half duplex * Flow control support for full duplex * Collision detection and auto retransmit on collisions in half duplex * Preamble generation and removal * Automatic 32 bit CRC generation and checking * Optional automatic Pad stripping on the receive packets. * Loopback support on the MII * Filtering modes supported on the Ethernet side: -- One 48 bit perfect address -- 64 hash-filtered multicast addresses -- Pass all multicast addresses -- Promiscuous Mode -- Pass all incoming packets with a status report -- Toss bad packets * Separate 32-bit status returned for transmit and receive packets -- Jumbo packet (0x2800 bytes) -- Big/Little Endian data format support
AMD AlchemyTM AU1500TM Processor Data Book
119
www..com
30361D Ethernet MAC Controller
The following PHY interfaces are supported: * MII - Ethernet 4-bit parallel PHY per IEEE 802.3u spec * MII Management - 2-wire bus to control and receive status from PHY * HPNA 1.0 support across MII The control registers for the MAC are used for address filtering, packet filter for good and bad frames, 48-bit MAC address with a local station address, a multicast table for filtering multicast frames and more. Each register is 32 bits wide.
7.4.1
Ethernet Registers
The two Ethernet MACs contained in the AU1500 processor are located at the base addresses shown in Table 7-11. In addition, the base addresses for the enable registers and the MAC DMA registers are shown.
Table 7-11. Ethernet Base Addresses
Name mac0_base mac1_base macen_base macdma0_base macdma1_base Physical Base Address 0x0 1150 0000 0x0 1151 0000 0x0 1152 0000 0x0 1400 4000 0x0 1400 4200 KSEG1 Base Address 0xB150 0000 0xB151 0000 0xB152 0000 0xB400 4000 0xB400 4200
7.4.2
MAC Registers
The Ethernet MAC registers are listed in Table 7-12.
Table 7-12. MAC Register Descriptions
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 Register Name mac_control mac_addrhigh mac_addrlow mac_hashhigh mac_hashlow mac_miictrl mac_miidata mac_flowctrl mac_vlan1 mac_vlan2 Description Operation Mode and Address Filter. High 16 bits of the MAC Physical Address. Lower 32 bits of the MAC Physical Address. High 32 bits of the Multicast Hash Address. Low 32 bits of the Multicast Hash Address. Control of PHY Management Interface. Data to be written or read from PHY over control interface. Control Frame Generation Control. VLAN1 Tag. VLAN2 Tag.
Note 1. Each Ethernet MAC has an identical register set with identical offsets from mac0_base and mac1_base. See Table 7-11 for base address.
120
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
7.4.2.1 MAC Control Register The MAC Control Register establishes the receive and transmit operating modes and controls for address filtering and packet filtering. Note that the PM, PR, IF, HP and HO bits in the MAC Control register will determine the address filtering mode. The RA, DB, PC and PB bits will determine the packet filter mode. The first bit of the destination address will determine if the address is a physical address (first bit = 0) or a multicast address (first bit = 1). If all bits in the destination address are set to 1 then the address is a broadcast address.
mac_control Offset = 0x0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RA EM DO LM F PM PR IF PB HO HP LC DB DR AP BL DC TE RE Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 31
Name RA
Description Receive All. 0 1 Normal Operation. All incoming packets will be received regardless of the destination address.
R/W R/W
Default 0
The address filter status is reported in Receive Status bit Filtering Fail. The Packet Filter bit in the Receive Status is set for all error-free frames regardless of the Destination Address field. 30 EM Endian Mode for Data Buffers. 0 1 29:24 23 -- DO Little endian. Big endian. R R/W 0 0 R/W 0
Reserved, should be cleared. Disable Receive Own. 0 1 The MAC receives all packets that are given by the PHY. The MAC disables reception of frames when the TXEN is asserted. The MAC ignores any loop backed receive packets.
This bit should be cleared when the full duplex mode bit is set or the Operating Mode is set to other than Normal Mode. 22:21 LM Loopback Operating Mode. 00 01 10 11 20 F 0 1 Normal Mode. Internal Loopback. External Loopback. Reserved. R/W 0 Half duplex mode. Full duplex mode. R/W 00
Full Duplex Mode.
Note: Be sure to disable both the transmitter and receiver before changing duplex modes. 19 PM Pass All Multicast. 0 1 Normal. All incoming frames with a multicast destination address (first bit in the destination address field is `1') are received and the Filter Fail bit reset. R/W 0
Incoming frames with physical address destinations are filtered according to HP (bit 13) and HO (bit 15). 18 PR Promiscuous Mode. 0 1 Normal Any incoming valid frame is received regardless of its destination address. R/W 1
The Filter Fail bit is always cleared in Promiscuous Mode.
AMD AlchemyTM AU1500TM Processor Data Book
121
www..com
30361D Ethernet MAC Controller
Bits 17
Name IF
Description Inverse Filtering. 0 1 Normal Physical addresses are checked with inverse filtering. In other words if the address passes a perfect address filter, the frame is not passed; if the address fails a perfect filter, the frame is passed.
R/W R/W
Default 0
This is valid only during perfect filtering mode. 16 PB Pass Bad Frames. 0 1 Normal All incoming frames that passed the address filtering are received including runt frames, collided frames, or truncated frames caused by buffer overflow. R/W 0
The Packet Filter bit is set for error frames that pass the Address filtering. If all received bad frames are required, promiscuous mode (bit 18) should be set. 15 HO Hash Only Filtering Mode. 0 1 Perfect address filtering mode for physical addresses Imperfect address filtering mode both for physical and multicast addresses R R/W 0 0 R/W 0
Setting this bit is valid only if HP=1. 14 13 -- HP Reserved, should be cleared. Hash/Perfect Filtering Mode 0 1 Address Check block does a perfect address filter of incoming frames according the address specified in the MAC Address register. Address Check block does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast Hash Table Register. If the Hash Only (HO) bit is set, then physical addresses are imperfectly filtered too. If the Hash Only bit (HO) is reset, then physical addresses are perfect address filtered according to the MAC Address Register. R/W 0 Abort frame transmission on a late collision. Enable the retransmission of the collided frame even after the collision period (late collision).
12
LC
Late Collision Control. 0 1
In either case the Late Collision Status is appropriately updated in the Transmit Packet Status. This bit is valid only when operating in half duplex mode. 11 DB Disable Broadcast Frames. 0 1 10 DR Forward all the broadcast frames to the application. (Packet Filter bit is set.) Disable the reception of broadcast frames. (Packet Filter bit is cleared.) R/W 0 The MAC will attempt 16 transmissions before signaling a retry error. The MAC will attempt transmission of a frame only once. When a collision is seen on the bus, the MAC will ignore the current frame and go to the next frame and a retry error will be reported in the Transmit Status. R 0 R/W 0
Disable Retry. 0 1
This bit is valid only when operating in half duplex mode. 9 -- Reserved, should be cleared.
122
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
Bits 8
Name AP
Description Automatic Pad Stripping. 0 1 Pass all the incoming frames to the host unmodified. Strip the pad field on all the incoming frames if the length field is less than 46 bytes. The FCS field is also stripped, because it is computed at the transmitting station based on the data and pad field characters and will therefore be invalid for a receive frame that has had the pad characters stripped. Receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified (FCS is not stripped).
R/W R/W
Default 0
Pad stripping is done only on the IEEE 802.3 formatted frames (frames with Length field). 7:6 BL Backoff Limit. The Backoff limit determines the integer number of slot times the MAC waits before rescheduling a transmission attempt (during retries after a collision). Deferral Check. 0 1 The deferral check is disabled in the MAC and the MAC defers indefinitely. The deferral check is enabled in the MAC. The MAC will abort the transmission attempt if it has deferred for more than 24,288 bit times. Deferring starts when the transmitter is ready to transmit, but is prevented from doing so because CRS is active. Defer time is not cumulative. In other words, if the transmitter defers, then transmits, collides, backs off, and then has to defer again after completion of backoff, the deferral timer resets to 0 and restarts. R R/W 0 0 R/W 00
5
DC
R/W
0
This bit is valid only when operating in half duplex mode. 4 3 -- TE Reserved, should be cleared. Transmitter Enable. 0 1 2 RE The MAC transmitter is disabled and will not transmit any frames on the MII interface. The MAC transmitter is enabled and it will transmit frames from the buffer on to the MII interface. R/W 0 The MAC receiver is disabled and will not receive any frames from the MII interface. The MAC receiver is enabled and will receive frames from the MII interface. R 0
Receiver Enable. 0 1
1:0
--
Reserved, should be cleared.
AMD AlchemyTM AU1500TM Processor Data Book
123
www..com
30361D Ethernet MAC Controller
7.4.2.2 MAC Address High and Low Registers The MAC Address High Register contains the upper 16 bits of the physical address of the MAC. The MAC Address Low Register contains the lower 32 bits of the physical address of the MAC. It is the responsibility of the system designer to provide the MAC address for the system. The MAC address will be compared with the destination address from the incoming frame with PADR[0] (bit 0 of the Mac Address Low register) being compared with the first bit of the destination address and PADR[47] (bit 15 of the MAC Address High register) compared with the 48th bit of the destination address. Example: To program the MAC address 00.50.c2.0c.20.10 the MAC address registers should be programmed as follows: mac_addrhigh = 0x00001020 mac_addrlow = 0x0CC25000
mac_addrhigh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Offset = 0x0004 3210 1 1 1 1
9876 PADR[47:32] 1111
5 1
4 1
Bits 31:16 15:0
Name -- PADR[47:32]
Description Reserved, should be cleared. Physical Address [47:32]. Contains the upper 16 bits (47 to 32) of the Physical Address of the MAC.
R/W R R/W
Default 0 0xFFFF
mac_addrlow Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PADR[31:0] Def. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 1
8 1
7 1
6 1
5 1
4 1
Offset = 0x0008 3210 1 1 1 1
Bits 31:0
Name PADR[31:0]
Description Physical Address [31:0]. Contains the lower 32 bits (31 to 0) of the Physical Address of the MAC.
R/W R/W
Default 0xFFFFFFFF
124
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
7.4.2.3 Multicast Address High and Low Hash Table Registers The 64-bit multicast address hash table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is passed through the CRC logic and the upper 6 bits of the CRC register are used to index the contents of the Hash table. The most significant bit determines the register to be used (1 = Hi, 0 = Low), while the other five bits determine the bit within the register. A value of `00000' selects the bit 0 of the selected register and a value of `11111' selects the bit 31 of the selected register. If the corresponding bit in the hash table is '1', then the multicast frame is accepted, otherwise it is rejected. If the Pass All Multicast is set, then all multi-cast frames are accepted regardless of the multi-cast hash values. The Multi Cast Hash Table High Register contains the higher 32 bits of the hash table and the Multi Cast Hash Table Low Register contains the lower 32 bits of the hash table.
mac_hashhigh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MCH[63:32] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000C 3210 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4 0
Bits 31:0
Name MCH[63:32]
Description Multicast Address Hash Table High. These bits map to the upper 32 bits of the 64 bit hash table.
R/W R/W
Default 0x00000000
mac_hashlow Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MCH[31:0] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
4 0
Offset = 0x0010 3210 0 0 0 0
Bits 31:0
Name MCH[31:0]
Description Multicast Address Hash Table Low. These bits map to the lower 32 bits of the 64 bit hash table.
R/W R/W
Default 0x00000000
AMD AlchemyTM AU1500TM Processor Data Book
125
www..com
30361D Ethernet MAC Controller
7.4.2.4 MII Control Register The MII Address Register is used to control and generate the Management cycles to the External PHY Controller chip. A write to this register will generate a read/write access on the MII Management Interface (MDIO/MDC) bus to an external PHY device.
mac_miictrl Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 PHYADDR[4:0] MIIREG[4:0] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0014 3210 MW MB 00000 4
5 0
Bits 31:16 15:11 10:6 5:2 1
Name -- PHYADDR MIIREG -- MW
Description Reserved, should be cleared. PHY Address. These bits tell which of the 32 possible PHY devices are being accessed. MII Register. These bits select the desired MII register in the selected PHY device. Reserved, should be cleared. MII Write. 0 1 Operation will be a read (data read is placed in MII Data Register) Operation will be a write (data to be written is taken from MII Data Register)
R/W R R/W R/W R R/W
Default 0 00000 00000 0 0
0
MB
MII Busy. This bit should read a logic 0 before writing to the MII address and MII data registers. This bit should be reset to 0 when writing to the MII address register. This bit will be set by the MAC to signify that a read or write access to the external PHY is in progress. For a write operation the data register should be kept valid until this bit is cleared by the MAC. For a read operation the MII data register is invalid until this bit is cleared by the MAC. The MII address register should not be modified until this bit is cleared. The MAC clears this bit after the PHY access is done.
R/W
0
7.4.2.5 MII Data Register The MII Data Register contains the data to be written to the PHY register specified in the MII address register, or it contains the read data from the PHY register whose address is specified in the MII address register.
mac_miidata Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0018 3210 0 0 0 0
9876 MIIDATA[15:0] 0000
5 0
4 0
Bits 31:16 15:0
Name -- MIIDATA
Description Reserved, should be cleared. MII Data 16-bit value read from the PHY after a MII read operation, or the 16bit data value to be written to the PHY before a MII write operation.
R/W R R/W
Default 0 0x0000
126
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
7.4.2.6 Flow Control Register This register is used to control the generation and reception of the Control (PAUSE Command) frames by the MAC's Flow control block. A write to this register with the busy bit set to `1' triggers the Flow Control block to generate a PAUSE Control frame. The fields of the control frame are selected as specified in the 802.3x specification with the Pause Time field from this register used in the "Pause Time" field of the control frame. The Busy bit will remain set until the control frame is transmitted. The Host has to insure that the Busy bit is cleared before writing to the register. The Pass Control Frames bit indicates to the MAC whether or not to pass the control frame to the Host. The Flow Control Enable bit enables the receive portion of the Flow Control block.
mac_flowctrl Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PT[15:0] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x001C 3210 PC FE FB 00000 4
9 0
8 0
7 0
6 0
5 0
Bits 31:16 15:3 2
Name PT -- PC
Description Pause Time. This field will be used in the PAUSE TIME field in the generation of the PAUSE control frame. Reserved, should be cleared. Pass Control Frame 0 The MAC decodes the control frames but does not pass the frames to the Host. The Control Frame bit in the Receive Status (bit 25) is set and the Transmitter Pause Mode signal gives the current status of the Transmitter, but the PacketFilter bit in the Receive Status is reset to signal the application to flush the frame. Control frames are passed to the Host. The MAC decodes the control frame (PAUSE) and disables the transmitter for the specified amount of time. The Control Frame bit in the Receive Status (bit 25) is set, and the Transmitter Pause Mode signal indicates the current state of the MAC Transmitter.
R/W R/W R R/W
Default 0x0000 0 0
1
1
FE
Flow Control Enable 0 1 The flow control operation in the MAC is disabled, and the MAC does not decode the frames for control frames. The MAC is enabled for flow control operation and it will decode all the incoming frames for control frames. If the MAC receives a valid control frame (PAUSE command), it will disable the transmitter for the specified time.
R/W
0
This bit is valid only in full duplex mode. 0 FB Flow Control Busy Status. This bit should read a logic 0 before writing to the Flow Control register. To initiate a PAUSE control frame the host must set this bit. During a transfer of Control Frame, this bit remains set to signify that a frame transmission is in progress. After the completion of PAUSE control frame transmission, the MAC clears FB. R/W 0
7.4.2.7
VLAN1 Tag Register
9876 VL1TAG[15:0] 1111 5 1 4 1 Offset = 0x0020 3210 1 1 1 1
mac_vlan1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bits 31:16 15:0
Name -- VL1TAG
Description Reserved, should be cleared. VLAN 1 Tag Identifier. This field will be compared with the 13th and 14th bytes of the incoming frame. If a nonzero match occurs the VLAN 1 Frame bit will be set in the receiver status packet. In addition, the legal length of a frame is increased from 1518 bytes to 1522 bytes.
R/W R R/W
Default 0 0xFFFF
AMD AlchemyTM AU1500TM Processor Data Book
127
www..com
30361D Ethernet MAC Controller
7.4.2.8
VLAN2 Tag Register
9876 VL2TAG[15:0] 1111 5 1 4 1 Offset = 0x0024 3210 1 1 1 1
mac_vlan2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bits 31:16 15:0
Name -- VL2TAG
Description Reserved, should be cleared. VLAN 2 Tag Identifier This field will be compared with the 13th and 14th bytes of the incoming frame. If a nonzero match occurs the VLAN 2 Frame bit will be set in the receiver status packet. In addition the legal length of a frame is increased from 1518 bytes to 1538 bytes.
R/W R R/W
Default 0 0xFFFF
7.4.3
MAC Enable Registers
Each Ethernet MAC has an identical enable register. Both enable registers are located off of the macen_base shown in Table 7-11 "Ethernet Base Addresses" on page 120. 7.4.3.1 MAC0 and MAC1 Enable The enable register for each MAC contains a bit that enables the entire block. The block should be disabled if not in use to minimize power consumption. In addition, each enable register contains a toss bit (TS) which prevents frames that do not pass the address filter from being put into memory. The process for bringing the MAC out of reset is as follows: 1) 2) Enable clocks (CE=1). Bring E[2:0] high together with the other bits configured as desired (keeping clocks enabled). MAC clocks must be running before the internal MAC registers are accessed.
Offset = 0x0000 Offset = 0x0004 76543210 JP E2 E1 C TS E0 CE 00000000
Note:
macen_mac0 macen_mac1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
Bits 31:7 6
Name -- JP
Description Reserved, should be cleared. Jumbo Packet Enable. 0 1 Normal (Max packet length = 0x800 bytes) Enable Jumbo Packet (Max packet length = 0x2800 bytes)
R/W W W
Default 0 0
5:4
E[2:1]
Enable field bits 2 and 1. Together with E0, this field resets and enables the MAC. 000 Reset 111 Enable All other combinations are invalid.
W
00
3
C
Coherent. 0 1 Memory accesses are marked coherent on SBUS Memory accesses are marked non coherent on SBUS
W
0
For more information on coherency see Section 2.8.2 "SBUS Coherency Model" on page 42.
128
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
Bits 2
Name TS
Description Disable Toss. 0 Only frames passing the address filter are passed to memory. Frames which fail length error, CRC error, or other non-address filter failures are still passed to memory. Frames are not passed to memory if the filter fail bit is set, or the frame is a broadcast frame and broadcast frames have been disabled. In promiscuous mode all frames are passed to memory unless the disable broadcast bit is set which prevents broadcast frames from being passed to memory. Frames that are not passed to memory are transparent to software-- no status or indication informs software. 1 All frames are passed to memory, regardless of address filter result.
R/W W
Default UNPRED
1 0
E[0] CE
Enable field bit 0. See description for E[2:1]. Clock Enable. 0 1 Clocks disabled to MAC Clocks enabled to MAC
W W
0 0
7.4.4
MAC DMA Registers
Each MAC has four DMA buffers for both receive and transmit (four for RX, four for TX). The DMA buffers are serviced in a round-robin fashion. Each MAC has a 32-word FIFO for both transmit and receive. The transfer size for the MAC DMA is eight WORDs. Both the FIFO size and transfer size are taken care of automatically by the MAC DMA and are transparent to the programmer except that all memory buffers must be implemented on a cache line boundary (32 bytes). The MAC DMA registers can be described as a set of transmit and receive entries off of the MAC DMA base addresses shown in Table 7-11 "Ethernet Base Addresses" on page 120. Each MAC DMA base address contains eight entries which correspond to four transmit buffer entries and four receive buffer entries as shown in Table 7-13.
Table 7-13. MAC DMA Entries
Offset (Note 1) 0x000 0x010 0x020 0x030 0x100 0x110 0x120 0x130 Note 1. See Table 7-11 on page 120 for base address. Entry Prefix tx0 tx1 tx2 tx3 rx0 rx1 rx2 rx3 Entry Name Transmit Buffer 0 Transmit Buffer 1 Transmit Buffer 2 Transmit Buffer 3 Receive Buffer 0 Receive Buffer 1 Receive Buffer 2 Receive Buffer 3
AMD AlchemyTM AU1500TM Processor Data Book
129
www..com
30361D Ethernet MAC Controller
Within each receive entry there are two registers implemented as shown in Table 7-14. (The third and fourth reserved entries are shown for completeness but are not used.)
Table 7-14. MAC DMA Receive Entry Registers
Offset 0x0 0x4 0x8 0xC Receive Entry Register stat addr Reserved Reserved Description Status register Address/enable register Nothing is implemented at this offset. Nothing is implemented at this offset.
Within each transmit entry, there are three registers implemented as shown in Table 7-15. (The fourth reserved entry is shown for completeness but is not used.)
Table 7-15. MAC DMA Transmit Entry Registers
Offset 0x0 0x4 0x8 0xC Transmit Entry Register stat addr len Reserved Description Status register Address/enable register Length register Nothing is implemented at this offset.
To calculate the address of a specific MAC DMA buffer all offsets should be combined. For example the physical address of the MAC1 receive buffer 3 address register is calculated as follows: macdma1_rx3addr = macdma1_base + rx3 + addr = 0x0 1400 4200 + 0x130 + 0x4 = 0x0 1400 4334 Another way to look at the DMA register addresses is to view them as built off of the base address using an indexed approach to build the address for each unique register within the block. In other words, each bit (or set of bits) within the address will select a parameter of the DMA Register (TX/RX, Buffer number, Status/Address/Length register) until a unique address is formed selecting a single register.
130
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
To build the address for a unique register the bits should be set according to the definitions in Table 7-16.
Table 7-16. MAC DMA Block Indexed Address Bit Definitions
AddrBits 8 Description TX/RX. 0 1 7:6 5:4 Transmit Block Receive Block
These bits should be cleared. MAC DMA Buffer. 00 Buffer 0 01 Buffer 1 10 Buffer 2 11 Buffer 3
3:2
Register Select 00 Status Register 01 Address/Enable Register 10 Length Register (valid for transmit only) 11 Reserved
1:0
These bits should be cleared because the registers are aligned on a word boundary.
The enumerated DMA registers are shown in Section A.1 "Memory Map" on page 255. 7.4.4.1 MAC DMA Receive Registers There are two receive registers for each DMA channel associated with each MAC: the status register and the address/ enable register. The length register is not applicable to the receive DMA channel, as the length will be determined by the size of the received packet (typically the size of a frame for a complete, successful reception). The receive memory buffers should be 0x800 bytes when Jumbo Packets are not enabled and to 0x2800 when Jumbo packets are enabled. This will allow for the worst case maximum reception length. In the naming of the receive registers dummy variables m and n have been inserted into the name to designate MAC number (m) and buffer number (n). Receive Status This register contains the receive packet status bits sent by the MAC after receiving a frame. This register is only valid after a receive transaction has been enabled by the host and the done bit has been set by the MAC in the Address/Enable Register to indicate that the transaction is complete. The MI bit should be checked by software after receiving a frame to verify that the received frame is valid.
macdmam_rxnstat Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 MI PF FF BF MF UC CF LE V2 V1 CR DB ME FT CS FL RF WT Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0 210 X X X
765 L[13:0] XXXX
8
4 X
3 X
Bits 31 MI
Name Missed Frame. 0 1
Description
R/W R
Default UNPRED
The frame is received normally by the Application without any latency or error violations Indicates that a frame was missed due to an internal FIFO overrun.
AMD AlchemyTM AU1500TM Processor Data Book
131
www..com
30361D Ethernet MAC Controller
Bits 30 PF
Name Packet Filter. 0 1
Description
R/W R
Default UNPRED
Indicates that the current frame failed the packet filter. Indicates that the current frame passed the packet filter that is implemented in the MAC.
Packet Filter will indicate failed frame when any of the following conditions happens. a. FF = 0 and frame is not a Broadcast or RA is 1 b. Frame is Broadcast and DB is 0 c. Frame is not Control Frame or PC is 1 d. No Error Status or PB Frames is 1 e. Unsupported Control Frame is 0 The Application can use this bit to decide whether to keep the packet in the memory or flush the packet from the memory. Note that frames with length greater than max Ethernet size (1500 bytesnormal, 1518 bytes - VLAN1, 1538 bytes - VLAN2) will create an error status thus failing the packet filter. The frames may still be valid with failure only due to frame size. 29 FF Filtering Fail. 0 1 28 BF Current frame passed address filtering Destination Address field in the current frame failed the Address filtering. R UNPRED Destination address is not Broadcast. Destination address is all 1's indicating broadcast address. R UNPRED Destination address is not multicast. Destination address is multicast (the first bit is 1). R UNPRED If the Control Frame bit is set, this bit indicates a supported control frame has been received (Pause Frame). The MAC observed an unsupported Control Frame. This is set when a control frame is received and the opcode field is unsupported, or the length is not equal to minFrameSize (64 bytes). This bit is set only when the MAC is operating in the full-duplex mode. R UNPRED Current frame is not a control frame. Current frame is a control frame. This bit is only set when operating in Full Duplex mode. R UNPRED No length error occurred. The current frame Length value is inconsistent with the total number of bytes received in the current frame. When the number of bytes received in the data field are more than what indicated in the Length/ Type field, the additional bytes are assumed to be PAD bytes and the Length Error bit is not set. When the number of bytes received in the data field is less than what was indicated in the Length/Type field, the Length Error bit is set. This is valid when the Frame Type is set to '0' (802.3 Frame). R UNPRED
Broadcast Frame. 0 1
27
MF
Multicast Frame. 0 1
26
UC
Unsupported Control Frame. 0 1
25
CF
Control Frame. 0 1
24
LE
Length Error. 0 1
This bit is not applicable for frame lengths greater than max Ethernet size (1500 bytes- normal, 1518 bytes - VLAN1, 1538 bytes - VLAN2). 23 V2 VLAN2 ID. 0 1 No match with VLAN2 tag The current frame is tagged with a VLAN2 ID. The thirteenth and fourteenth bytes of the frame were a nonzero match with the VLAN2 tag register. AMD AlchemyTM AU1500TM Processor Data Book R UNPRED
132
www..com
Ethernet MAC Controller 30361D
Bits 22 V1
Name VLAN1 ID. 0 1
Description
R/W R
Default UNPRED
No match with VLAN1 tag The current frame is tagged with a VLAN1 ID. The thirteenth and fourteenth bytes of the frame were a nonzero match with the VLAN1 tag register. R UNPRED No CRC error in current frame CRC error occurred in received frame.
21
CR
CRC Error. 0 1
This bit is not applicable for frame lengths greater than max Ethernet size (1500 bytes- normal, 1518 bytes - VLAN1, 1538 bytes - VLAN2). If a CRC check is required it must be done in software. 20 DB Dribbling Bit. 0 1 An integer multiple of eight bits was received. A non-integer multiple of eight bits was received. This bit is not valid if either the Collision Seen bit or Runt Frame bit is set. If this bit is set and the CRC Error bit is 0, then the packet is still valid. R UNPRED No MII error. MII error during frame reception. R UNPRED IEEE 802.3 Frame. Ethernet-type frame (frame length field is greater than max Ethernet size (1500 bytes- normal, 1518 bytes - VLAN1, 1538 bytes - VLAN2). R UNPRED
19
ME
MII Error. 0 1
18
FT
Frame Type. 0 1
This bit is still applicable when Jumbo packets are enabled. This bit is not valid for runt frames of less than 14 bytes. 17 CS Collision Seen. 0 1 No collision seen during frame reception. The frame was damaged by a collision that occurred after the 64 bytes following the start of frame delimiter (SFD). This is a late collision. R UNPRED Frame size is less than or equal to max Ethernet frame size (1500 bytes- normal, 1518 bytes - VLAN1, 1538 bytes - VLAN2). Frame size is greater than the maximum Ethernet specified size (1500 bytes- normal, 1518 bytes - VLAN1, 1538 bytes - VLAN2). This also applies when Jumbo packets are enabled. R UNPRED
16
FL
Frame Too Long. 0 1
Frame too long is only a length indication and does not cause frame truncation. 15 RF Runt Frame. 0 1 14 WT Frame was not damaged in collision window. Frame was damaged by a collision or premature termination before the collision window passed. R UNPRED Frame was received before timeout occurred. The receive watchdog timer expired while receiving the frame. The watchdog timer inside the MAC is programmed to be twice the MaxFrameLength. When set, the Frame Length field is invalid. R UNPRED
Watchdog Timeout. 0 1
Any time the max frame length is exceeded (0x800 bytes for normal mode, 0x2800 with Jumbo packets enabled) the WT bit will be set. 13:0 L[13:0] Frame Length. Indicates length in bytes of the received frame. The host should take into account how the Automatic Pad Stripping (AP) bit in the corresponding MAC control register is set, as this will affect how the length field and frame contents should be interpreted. R UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
133
www..com
30361D Ethernet MAC Controller
Receive Buffer Address/Enable Register This register contains the starting address for the receive buffer. The host should ensure that the memory buffer is set up to accommodate the worst case largest frame size to be able to handle all received packets. At worst case the MAC will receive 0x800 bytes before aborting a receive in normal mode or 0x2800 bytes when Jumbo packets have been enabled in the macen_macn register. After the transaction has been enabled this register should not be written until the DN bit has been set. The buffer for the DMA must be cache line aligned so the lowest 5 bits are not used as part of the address. These bits have been employed as done and enable bits that are exclusive of the address.
macdmam_rxnaddr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR[31:5] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x4 3210 CB DN EN XXXX
9 0
8 0
7 0
6 0
5 0
4 0
Bits 31:5
Name ADDR
Description Buffer Address. Upper 27 bits of the starting physical address for the DMA buffer. This address must be cache line (32 bytes) aligned so only 27 bits are used. This address must be written for each DMA transaction (the address will not remain after the transaction is enabled) Reserved, should be cleared. Current Buffer. Current DMA Receive Buffer Transaction Done. This bit will be set by hardware to indicate that the receive transaction has been completed and that the receive packet status is valid. If the respective MAC DMA interrupt is enabled (see Section 6.0 "Interrupt Controller" on page 95), an interrupt will be generated when this bit is set. Done bits for all TX and RX buffers are or'ed together for this interrupt so a high level interrupt should be used. This bit must be cleared explicitly by software after checking for done. This will also clear the interrupt.
R/W R/W
Default 0
4 3:2 1
-- CB DN
R R R/W
0 UNPRED UNPRED
0
EN
MAC DMA Enable. When set, this bit enables a DMA receive transaction to the memory location designated in ADDR.
R/W
UNPRED
7.4.4.2 MAC DMA Transmit Registers There are three transmit registers, including the status register, the address/enable register, and the length register. In the naming of the receive registers dummy variables m and n have been inserted into the name to designate MAC number (m) and buffer number (n). Transmit Packet Status Register This register contains the transmit packet status bits sent by the MAC after transmitting a frame. This register is valid after a transmit transaction has been enabled by the host and the done bit has been set by the MAC in the Address/Enable Register to signify that the transmit transaction is complete. If either PR (bit 31) or FA (bit 0) is set then the frame was not sent successfully and the application should resend the frame.
macdmam_txnstat Offset = 0x0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR CC LO DF UR EC LC ED LS NC JT FA Def. X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
134
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
Bits 31
Name PR
Description Packet Retry. 0 1 Transmission of current packet is complete. The Application has to restart the transmission of the frame (packet) when this bit is set to `1'. The successful/unsuccessful completion of the frame's transmission is indicated by the Frame Aborted bit (bit 0).
R/W R
Default UNPRED
30:14 13:10
-- CC
These bits are reserved. Collision Count. This 4-bit count indicates the number of collisions that occurred before the frame was transmitted. This bit is not valid when the Excessive Collisions bit is set. This bit is valid only when the MAC is operating in half-duplex mode.
R R
UNPRED UNPRED
9
LO
Late Collision Observed. 0 1 No late collision observed during transmission. Indicates that the MAC observed a late collision (collision after 64 bytes into transmission of frame), but retransmitted the frame in the next retransmission attempt. This bit will be set when the Late Collision bit is set.
R
UNPRED
This bit is valid only when the MAC is operating in half-duplex mode. 8 DF Deferred. 0 1 7 UR Transmitter did not defer when transmitting. The transmitter had to defer while ready to transmit a frame. R UNPRED R UNPRED
This bit is valid only when operating in half-duplex mode. Under Run. 0 1 6 EC No data under run. The transmitter aborted the message because of data under run during the frame's transmission. R UNPRED Transmission did not abort due to excessive collisions. Transmission aborted after 16 successive collisions. If the Disable Retry bit is set, this bit is set after the first collision and the transmission of the frame will be aborted. R UNPRED
Excessive Collisions. 0 1
This bit is valid only when operating in half-duplex mode. 5 LC Late Collision. 0 1 No late collision. Transmission was aborted due to collision occurring after the collision window of 64 bytes. This bit is not valid if under run error is set. R UNPRED
This bit is valid only when operating in half-duplex mode. 4 ED Excessive Deferral. 0 1 No excessive deferral. Transmission has ended because of excessive deferral of over 24,288 bit times during the transmission, if the defer bit is set high in the control register. R UNPRED
This bit is valid only when operating in half-duplex mode. 3 LS Loss of Carrier. 0 1 No loss of carrier. The loss of carrier occurred during the frame's transmission (i.e., the CRS input was inactive for one or more bit times when the frame is being transmitted).
This bit is valid only when operating in half-duplex mode.
AMD AlchemyTM AU1500TM Processor Data Book
135
www..com
30361D Ethernet MAC Controller
Bits 2
Name NC
Description No Carrier. 0 1 Carrier present The carrier signal from the transceiver was not present during transmission.
R/W R
Default UNPRED
This bit is valid only when operating in half-duplex mode. 1 JT Jabber Timeout. 0 1 0 FA No jabber timeout. The MAC transmitter has been active for an abnormally long time (twice the Ethernet maxFrameLength size). R UNPRED Current frame was successfully transmitted. The transmission of the current frame has been aborted by the MAC because of one or more of the following conditions: R UNPRED
Frame Aborted. 0 1
Jabber Timeout (bit 1) No Carrier (bit 2) Loss of Carrier (bit 3) Excessive Deferral (bit 4) Late Collision (bit 5) Retry Count exceeds the attempt limit (bit 6). Data under run (bit 7)
Transmit Buffer Address/Enable Register This register contains the starting address for the transmit memory buffer. The MAC DMA transfers the number of bytes designated in the Length register. The buffer for the DMA must be cache line aligned so the lowest 5 bits are not used as part of the address. These bits have been employed as done and enable bits and are exclusive of the address.
macdmam_txnaddr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR[31:5] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x4 3210 CB DN EN XXX0
9 0
8 0
7 0
6 0
5 0
4 0
Bits 31:5
Name ADDR
Description Buffer Address. Upper 27 bits of the starting physical address for the DMA buffer--but not including the most significant nibble address bits 35:32. This address must be cache line (32 bytes) aligned so only 27 bits are used. Note: This address must be written for each DMA transaction (the address will not remain after the transaction is enabled).
R/W R/W
Default 0
4 3:2 1
-- CB DN
Reserved, should be cleared. Current Buffer. Current DMA Transmit Buffer Transaction Done. This bit will be set by hardware to indicate that the transmit transaction has been completed and that the transmit packet status is valid. If the respective MAC DMA interrupt is enabled (see Section 6.0 "Interrupt Controller" on page 95), an interrupt will be generated when this bit is set. Done bits for all TX and RX buffers are or'ed together for this interrupt so a high level interrupt should be used. This bit must be cleared explicitly by software after checking for done. This will also clear the interrupt.
R R R/W
0 UNPRED UNPRED
0
EN
MAC DMA Enable. When set, this bit enables a DMA transmit transaction from the memory location designated in ADDR.
R/W
136
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
Transmit Buffer Length Register This register contains the length of the memory buffer in bytes to be transmitted.
macdmam_txnlen Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x8 210 0 0 0
9 0
765 LEN[13:0] 0000
8
4 0
3 0
Bits 31:14 13:0
Name -- LEN
Description Reserved, should be cleared. Buffer Length. This field sets the length of the memory buffer (in bytes). When the normal bit is set the length can only be up to 0x800 bytes. When the Jumbo packets are enabled in the enable register the length can be set up to 0x2800 bytes.
R/W R R/W
Default 0 0
7.4.5
Hardware Connections
Table 7-17 shows the signals associated with the two Ethernet MAC MII interfaces.
Table 7-17. Ethernet Signals
Signal Input/Output Description
Ethernet Controller 0 (MAC0) N0TXCLK N0TXEN N0TXD[3:0] I O O Continuous clock input for synchronization of transmit data. 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Indicates that the data nibble on N0TXD[3:0] is valid. Nibble wide data bus synchronous to N0TXCLK. For each N0TXCLK period in which N0TXEN is asserted, TXD[3:0] will have the data to be accepted by the PHY. While N0TXEN is de-asserted the data presented on TXD[3:0] should be ignored. Continuous clock that provides the timing reference for the data transfer from the PHY to the MAC. N0RXCLK is sourced by the PHY. The N0RXCLK shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 MHz at 100 Mbs and 2.5 MHz at 10 Mbs). Active high. Indicates that a receive frame is in process and that the data on N0RXD[3:0] is valid. RXD[3:0] is a nibble wide data bus driven by the PHY to the MAC synchronous with N0RXCLK. For each N0RXCLK period in which N0RXDV is asserted, RXD[3:0] will transfer four bits of recovered data from the PHY to the MAC. While N0RXDV is deasserted, RXD[3:0] will have no effect on the MAC. N0CRS shall be asserted by the PHY when either transmit or receive medium is non Idle. N0CRS shall be deasserted by the PHY when both the transmit and receive medium are Idle. N0CRS is an asynchronous input. N0COL shall be asserted by the PHY upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. N0COL is an asynchronous input. The N0COL signal is ignored by the MAC when operating in the full duplex mode. N0MDC is sourced by the MAC to the PHY as the timing reference for transfer of information on the N0MDIO signal. N0MDC is an aperiodic signal that has no maximum high or low times. The N0MDC frequency is fixed at SBUS clock divided by 160. N0MDIO is the bidirectional data signal between the MAC and the PHY that is clocked by N0MDC.
137
N0RXCLK
I
N0RXDV N0RXD[3:0]
I I
N0CRS
I
N0COL
I
N0MDC
O
N0MDIO
I/O
AMD AlchemyTM AU1500TM Processor Data Book
www..com
30361D Ethernet MAC Controller
Table 7-17. Ethernet Signals (Continued)
Signal Input/Output Description
Ethernet Controller 1 (MAC1) N1TXCLK N1TXEN I O Continuous clock input for synchronization of transmit data. 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Active high. Indicates that the data nibble on N1TXD[3:0] is valid. Muxed with GPIO[24]. GPIO[24] is the default signal coming out of hardware reset, runtime reset, and Sleep. N1TXD[3:0] O Nibble wide data bus synchronous to N1TXCLK. For each N1TXCLK period in which N1TXEN is asserted, TXD[3:0] will have the data to be accepted by the PHY. While N1TXEN is de-asserted the data presented on TXD[3:0] should be ignored. Muxed with GPIO[28:25]. GPIO[28:25] are the default signals coming out of hardware reset, runtime reset, and Sleep. N1RXCLK I Continuous clock that provides the timing reference for the data transfer from the PHY to the MAC. N1RXCLK is sourced by the PHY. The N1RXCLK shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps) Active high. Indicates that a receive frame is in process and that the data on N1RXD[3:0] is valid. RXD[3:0] is a nibble wide data bus driven by the PHY to the MAC synchronous with N1RXCLK. For each N1RXCLK period in which N1RXDV is asserted, RXD[3:0] will transfer four bits of recovered data from the PHY to the MAC. While N1RXDV is deasserted, RXD[3:0] will have no effect on the MAC. N1CRS shall be asserted by the PHY when either transmit or receive medium is non Idle. N1CRS shall be deasserted by the PHY when both the transmit and receive medium are Idle. N1CRS is an isochronous input. N1COL shall be asserted by the PHY upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. N1COL is an asynchronous input. The N1COL signal is ignored by the MAC when operating in the full duplex mode. N1MDC is sourced by the MAC to the PHY as the timing reference for transfer of information on the N1MDIO signal. N1MDC is an aperiodic signal that has no maximum high or low times. The N1MDC frequency is fixed at SBUS clock divided by 160. N1MDIO is the bidirectional data signal between the MAC and the PHY that is clocked by N1MDC.
N1RXDV N1RXD[3:0]
I I
N1CRS
I
N1COL
I
N1MDC
O
N1MDIO
I/O
MAC1 shares its pins with GPIO[28:24]; these pins must be assigned to MAC1 in order to use MAC1. Please see Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168 for more information.
138
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Ethernet MAC Controller 30361D
7.4.6
Programming Considerations
The Ethernet MAC is designed such that the application could use a pool of memory buffers for both the transmit and receive functions. The lowest level device driver would respond to the MAC DMA interrupt and swap out the filled DMA buffers for those that are empty for the receive case. For the transmit case the driver should provide ready to transmit buffers to the DMA while reclaiming empty buffers. Four transmit and receive DMA buffers are allocated for each MAC to allow for latency to service the lowest level MAC DMA interrupt. At the next level in software the device driver can parse the valid data out of the frame for receive, or build the frame for transmit. The number of memory buffers needed in the pool will depend on how fast the parsing can occur for worst case receive bursts, and any minimum transmit latency requirements. From this level the application or protocol stack can take the data and apply it as needed.
7.4.7
Initialization
This section demonstrates the functional requirements for getting the MAC running. This assumes that the programmer has already performed the AU1500 bringup. 1) 2) 3) 4) Interrupt Controller - a high level interrupt should be used as the interrupt is triggered with an OR'ing of the DN (Done) bits. DMA Controller Setup MAC Registers - It is the system designer's responsibility to set up addresses. Memory - Depending on how the system is built, there could be a pool of memory buffers which can be used for parsing and building of frames. Individual buffers would be swapped in and out of the 4 active receive and transmit DMA buffers as needed. This strategy would require some sort of minimal memory management within the Ethernet driver to insure chronology of Ethernet frames.
The following is a transmit example in a basic form. Typically this would be split between an interrupt handler and another higher layer. 1) 2) 3) 4) 5) Construct Frame Set length in macdmam_txnlen register Set address of memory buffer and enable transmit. During this time the physical memory buffer and address and length registers should not be disrupted or transmit contents will be undefined. Wait for done. This can be done by waiting for the interrupt handler or polling the done signal in the macdmam_txnaddr register. Read status. Its validity is signaled by the reception of the done signal.
The following is a basic receive example: 1) 2) 3) 4) 5) Enable all receive buffers with four different memory buffer addresses. Wait for interrupt. Conversely the done bit could be polled. During this time the physical memory buffer and address registers should not be disrupted or receive contents will be undefined. Replace all full buffers with empty memory buffers. Read Status for full buffers. Parse frames.
AMD AlchemyTM AU1500TM Processor Data Book
139
www..com
30361D UART Interfaces
7.5
UART Interfaces
The AU1500 contains two UART interfaces. Each UART has the following features: * 5 - 8 Data Bits * 1 - 2 Stop Bits * Even, Odd, Mark, or No Parity * 16-byte Transmit and Receive FIFOs * Interrupts for Receive FIFO Full, Half Full, and Not Empty * Interrupts for Transmit FIFO Empty * False Start Bit Detection * Full Modem Control Signals on UART3 * Capable of speeds up to 1.5 Mbps to enable connections with Bluetooth and other peripherals through a UART interface * Similar to personal computer industry standard 16550 UART
7.5.1
Programming Model
Each UART is controlled by a register block. Table 7-18 lists the base address for each UART register block.
Table 7-18. UART Register Base Addresses
Name uart0_base uart3_base Physical Base Address 0x0 1110 0000 0x0 1140 0000 KSEG1 Base Address 0xB110 0000 0xB140 0000
UART0 and UART3 are capable of being used with DMA. See Section 5.0 "DMA Controller" on page 87 for more information.
7.5.2
UART Registers
Each register block contains the registers listed in Table 7-19.
Table 7-19. UART Registers
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0100 Register Name uart_rxdata uart_txdata uart_inten uart_intcause uart_fifoctrl uart_linectrl uart_mdmctrl uart_linestat uart_mdmstat uart_autoflow uart_clkdiv uart_enable Description Received Data FIFO Transmit Data FIFO Interrupt Enable Register Pending Interrupt Cause Register FIFO Control Register Line Control Register Modem Line Control Register (UART3 only) Line Status Register Modem Line Status Register (UART3 only) Automatic Hardware Flow Control (UART3 only) Baud Rate Clock Divider Module Enable Register
Note 1. See Table 7-18 for base address.
140
AMD AlchemyTM AU1500TM Processor Data Book
www..com
UART Interfaces 30361D
7.5.2.1 Received Data FIFO The uart_rxdata register contains the next entry in the received data FIFO. This register is read only.
uart_rxdata - Received Data FIFO Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0000 43210 RXDATA 000000 5
9 0
8 0
7 0
6 0
Bits 31:8 7:0
Name -- RXDATA
Description Reserved, should be cleared. Receive Data
R/W R R
Default 0 0
7.5.2.2 Transmit Data FIFO The uart_txdata register provides access to the transmit data FIFO. This register is write only.
uart_txdata - Transmit Data FIFO Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0004 43210 TXDATA 000000 5
9 0
8 0
7 0
6 0
Bits 31:8 7:0
Name -- TXDATA
Description Reserved, should be cleared. Transmit Data
R/W R R
Default 0 0
7.5.2.3 Interrupt Enable Register The uart_inten register contains bits which enable interrupts under certain operational conditions.
uart_inten - Interrupt Enable Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0008 3210 MIE LIE TIE RIE 00000 4
9 0
8 0
7 0
6 0
5 0
Bits 31:4 3
Name -- MIE
Description Reserved, should be cleared. Modem Status Interrupt Enable (UART3 only). When the MIE bit is set an interrupt is generated when changes occur in the state of the optional modem control signals available with UART3. System Note: For systems that use the UART3 interface but do not use the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (MIE=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as a general-purpose system input.
R/W R R/W
Default 0 0
2 1 0
LIE TIE RIE
Line Status Interrupt Enable. When the LIE bit is set an interrupt is generated when errors (overrun, framing, stop bits) or break conditions occur. Transmit Interrupt Enable. When the TIE bit is set an interrupt is generated when the transmit FIFO is not full. Receive Interrupt Enable. When the RIE bit is set the UART will generate an interrupt on received data ready (DR bit in the uart_linestat register) or a character time out.
R/W R/W R/W
0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
141
w
w
w
.
D
a
t
a
S
h
e
e
t
4
U
.
c
o
m
UART Interfaces
30361D
7.5.2.4 Interrupt Cause Register The uart_intcause register contains information about the cause of the current interrupt.
uart_intcause - Interrupt Cause Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000c 3210 IID IP 00001 4
9 0
8 0
7 0
6 0
5 0
Bits 31:4 3:1
Name -- IID
Description Reserved, should be cleared. Interrupt Identifier. The IID field identifies the highest priority current interrupt condition. Table 7-20 "Interrupt Cause Encoding" lists the priorities and encodings of each interrupt condition. No Interrupt Pending. 0 1 An interrupt is pending. No interrupts are pending.
R/W R R
Default 0 0
0
IP
R
1
Table 7-20 contains information about the interrupt cause encoding.
Table 7-20. Interrupt Cause Encoding
IID 0 1 2 Priority 5 (lowest) 4 3 Type Modem Status Transmit Buffer Available Receive Data Available Source DD, TRI, DR or DC of uart_mdmstat TT of uart_linestat The receive FIFO having greater than RFT (of uart_fifoctrl) bytes in it if FIFOs are enabled. DR of uart_linestat if FIFOs are disabled. 3 4 5 6 7 2 1 (highest) Receive Line Status Reserved Reserved Character Time Out Reserved Character has been in receive FIFO for 0x300 UART clocks (set by uart_clkdiv) OE, PE, FE, BI in uart_linestat register
142
AMD AlchemyTM AU1500TM Processor Data Book
www..com
UART Interfaces 30361D
7.5.2.5 FIFO Control Register The uart_fifoctrl register provides control of character buffering options.
uart_fifoctrl - FIFO Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0010 543210 TFT MS TR RR FE 000000
9 0
8 0
76 RFT 00
Bits 31:8 7:6
Name -- RFT
Description Reserved, should be cleared. Receive FIFO Threshold. A receive threshold interrupt is generated when the number of characters in the receiver FIFO is greater than or equal to the trigger level listed below: 00 01 10 11 Trigger depth = 1 Trigger depth = 4 Trigger depth = 8 Trigger depth = 14
R/W R R/W
Default 0 0
If using DMA it is important that the receive FIFO threshold and transmit FIFO threshold are the same and programmed consistently with the transfer size for the DMA channel being used. See Section 5.0 "DMA Controller" on page 87 for more information. 5:4 TFT Transmit FIFO Threshold. A transmit threshold interrupt is generated if the number of valid characters contained in the transmit FIFO is less than or equal to the trigger depth. The encoding of trigger depth for each value of TFT is shown below: 00 01 10 11 Trigger depth = 0 Trigger depth = 4 Trigger depth = 8 Trigger depth = 12 R/W 0
If using DMA it is important that the receive FIFO threshold and transmit FIFO threshold are the same and programmed consistently with the transfer size for the DMA channel being used. See Section 5.0 "DMA Controller" on page 87 for more information. 3 MS Mode Select. If the MS bit is clear interrupts are generated by the receiver when any data is available and by the transmitter when there is no data to transmit. Setting the MS bit causes interrupts to be generated based on FIFO threshold levels. Transmitter Reset. Writing a one to the TR bit will clear the transmit FIFO and reset the transmitter. The transmit shift register is not cleared. Receiver Reset. Writing a one to the RR bit will clear the receiver FIFO and reset the receiver. The receiver shift register is not cleared. FIFO Enable. The FE bit enables the 16 byte FIFOs on transmit and receive. When the FE bit is clear both FIFOs will have an effective depth of 1 byte. R/W 0
2 1 0
TR RR FE
R/W R/W R/W
0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
143
www..com
30361D UART Interfaces
7.5.2.6 Line Control Register The uart_linectrl register provides control over the data format and parity options.
uart_linectrl - Line Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0014 6543210 SB PAR PE ST WLS 00000000 7
9 0
8 0
Bits 31:7 6 5:4
Name -- SB PAR
Description Reserved, should be cleared. Send Break. Setting the SB bit will force the transmitter output to zero. Parity Select. Selects the parity encoding for the transmitter and receiver. 00 01 10 11 Odd parity Even parity Mark parity Zero parity
R/W R R/W R/W
Default 0 0 0
3 2
PE ST
Parity Enable. If the PE bit is clear parity will not be sent or expected. If the PE bit is set parity is selected according to the PAR field. Stop Bits. If the ST bit is clear one stop bit is sent and expected. Setting the ST bit selects 1.5 stop bits for 5 bit characters and 2 stop bits for all other character lengths. Word Length Select. The WLS field selects the number of data bits in each character. The number of bits is WLS+5.
R/W R/W
0 0
1:0
WLS
R/W
0
7.5.2.7 Modem Control Register The uart_mdmctrl register allows the state of the output modem control signals to be set. The external modem signals are only available on UART3.
uart_mdmctrl - Modem Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0018 43210 LB I1 I0 RT DT 000000 5
9 0
8 0
7 0
6 0
Bits 31:5 4
Name -- LB
Description Reserved, should be cleared. Loopback. 0 1 No loopback (normal operation) Enable loopback for self-test. Establish the internal connections shown below: Output Signal TXD DTR# RTS# I0# I1# Looped Back To RXD DSR# CTS# RI# DCD#
R/W R R/W
Default 0 0
3 2 1
I1 I0 RT
Internal Line 1 State. When the I1 bit is set the internal I1# line for this port is driven low. This can be used in loopback mode. Internal Line 0 State. When the I0 bit is set the external I0# line for this port is driven low.This can be used in loopback mode. Request To Send. When the RT bit is set the external RTS# line for this port is driven low. Note: This bit has no effect if uart_autoflow[AE] is set. Data Terminal Ready. When the DT bit is set the external DTR# line for this port is driven low.
R/W R/W R/W
0 0 0
0
DT
R/W
0
144
AMD AlchemyTM AU1500TM Processor Data Book
www..com
UART Interfaces 30361D
7.5.2.8 Line Status Register The uart_linestat register reflects the state of the interface. Bits in this register are set when the listed condition and cleared when this register is read.
uart_linestat - Line Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x001C 76543210 RF TE TT BI FE PE OE DR 000000000 8
9 0
Bits 31:8 7 6 5
Name -- RF TE TT
Description Reserved, should be cleared. Receiver FIFO Contains Error. This bit is set when one of the characters in the receive FIFO contains a parity error, framing error, or break indication. Transmit Shift Register Empty. This bit is set when the transmit shift register is empty and there are no more characters in the FIFO. Transmit Threshold. This bit is set when the transmitter FIFO depth is less than or equal to the value of the TFT field in the FIFO control register. When FIFOs are not enabled this bit is set when the transmitter data register is empty
R/W R R R R
Default 0 0 0 0
4
BI
Break Indication. This bit is set if a break is received. When a break is detected a single zero character is received. The BI bit is valid when the zero character is at the top of the receive FIFO. This bit must be cleared with a read to uart_linestat before more characters are received. Framing Error. The FE bit is set when a valid stop bit is not detected. This bit reflects the state of the character at the top of the receive FIFO. The FE bit is cleared by a read to uart_linestat. Parity Error. The PE bit is set when the received character at the top of the FIFO contains a parity error. This bit is cleared by reading uart_linestat. Overrun Error. The OE bit is set when a receiver overrun occurs. This bit is cleared when uart_linestat is read. Data Ready. The DR bit is set when the receive FIFO contains valid characters.
R
0
3
FE
R
0
2 1 0
PE OE DR
R R R
0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
145
www..com
30361D UART Interfaces
7.5.2.9 Modem Status Register The uart_mdmstat register reflects the state of the external modem signals. Reading this register will clear any delta indications and the corresponding interrupt. The external modem signals are optional and are present only on UART3.
uart3_mdmstat - Modem Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0020 76543210 CD RI DS CT DD TRI DR DC 000000000 8
9 0
Bits 31:8 7 6 5 4 3 2 1 0
Name -- CD RI DS CT DD TRI DR DC
Description Reserved, should be cleared. Data Carrier Detect. The CD bit reflects the status of the external DCD# pin. Ring Indication. The RI bit reflects the status of the external RI# pin. Data Set Ready. The DS bit reflects the status of the external DSR# pin. Clear To Send. The CT bit reflects the status of the external CTS# pin. Delta DCD. The DD bit is set when a change occurs in the state of the external DCD# pin. Terminate Ring Indication. The TRI bit is set when a positive edge occurs in the state of the external RI# pin. Delta DSR. The DR bit is set when a change occurs in the state of the external DSR# pin. Delta CTS. The DC bit is set when a change occurs in the state of the external CTS# pin.
R/W R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0
7.5.2.10 Automatic Hardware Flow Control Register The uart_autoflow register controls automatic hardware flow control using modem control signals CTS# and RTS#. Upon enabling this mode, internal logic controls the output signal RTS# based upon the data register state and threshold levels. The internal logic asserts RTS (low) to request data until the internal receive FIFO reaches its preset threshold. In this mode RTS# cannot be controlled with the uart_mdmctrl[RT] bit. The input signal CTS# controls the transmission of data by loading the transmit shift register from the data register only while CTS# is asserted (low). Once the transmit shift register is loaded with data, it sends the entire character regardless of the CTS# signal state.
uart_autoflow - Automatic Hardware Flow Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0024 3210 AE 00000 4
9 0
8 0
7 0
6 0
5 0
Bits 31:1 0
Name -- AE
Description Reserved, should be cleared. Autoflow Enable. Setting this bit enables automatic hardware flow control on UART3. Enabling this mode overrides software control of the signals.
R/W R R/W
Default 0 0
146
AMD AlchemyTM AU1500TM Processor Data Book
www..com
UART Interfaces 30361D
7.5.2.11 Clock Divider Register The uart_clkdiv register contains the divider used to generate the baud rate clock. The input to the UART clock divider is the internal peripheral bus clock, which is derived from the System Bus (SBUS) clock; see Figure 8-1 "Clocking Topology" on page 154.
uart_clkdiv - Clock Divider Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0028 3210 0 0 0 1
876 CLKDIV 0000
9
5 0
4 0
Bits 31:16 15:0
Name -- CLKDIV
Description Reserved. Clock Divider. The baud rate of the interface is computed as follows: Baud rate = CPU / (SD * 2 * CLKDIV * 16) CPU: SD: CPU clock SBUS divider
R/W -- R/W
Default -- 0x1
See Section 8.4 "Power Management" on page 172 for information on changing SD.
7.5.2.12 UART Enable The uart_enable register controls reset and clock enable to the UART The correct routine for bringing the USB Device out of reset is as follows: 1) 2) Set the CE bit to enable clocks. Set the E bit to enable the peripheral.
Offset = 0x0100 3210 E CE 00000 4
uart_enable - UART Enable Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
Bits 31:2 1 0
Name -- E CE
Description Reserved, should be cleared. Enable. When the E bit is clear the entire module is held in reset. After enabling clocks, this bit should be set to enable normal operation. Clock Enable. When the CE bit is clear the module clock source is inhibited. This can be used to place the module in a low power Stand-by state. The CE bit should be set before the module is enabled for proper bringup.
R/W R R/W R/W
Default 0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
147
www..com
30361D UART Interfaces
7.5.3
Hardware Considerations
The UART signals are listed in Table 7-21. For changing pin functionality please refer to the sys_pinfunc register in Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168.
Table 7-21. UART Signals
Signal UART0 U0TXD U0RXD UART3 U3TXD U3RXD U3CTS# O I I UART3 Transmit. Muxed with GPIO[23]. GPIO[23] is the default signal coming out of hardware reset, runtime reset, and Sleep. UART3 Receive. Clear to Send (optional). Muxed with GPIO[9]. GPIO[9] is the default signal coming out of hardware reset, runtime reset, and Sleep. System Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input. U3DSR# I Data Set Ready (optional). Muxed with GPIO[10]. GPIO[10] is the default signal coming out of hardware reset, runtime reset, and Sleep. System Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input. U3DCD# I Data Carrier Detect (optional). Muxed with GPIO[11]. GPIO[11] is the default signal coming out of hardware reset, runtime reset, and Sleep. System Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input. U3RI# I Ring Indication (optional). Muxed with GPIO[12]. GPIO[12] is the default signal coming out of hardware reset, runtime reset, and Sleep. System Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input. U3RTS# U3DTR# O O Request to Send (optional). Muxed with GPIO[13]. GPIO[13] is the default signal coming out of hardware reset, runtime reset, and Sleep. Data Terminal Ready (optional). Muxed with GPIO[14]. GPIO[14] is the default signal coming out of hardware reset, runtime reset, and Sleep. O I UART0 Transmit. Muxed with GPIO[20]. GPIO[20] is the default signal coming out of hardware reset, runtime reset, and Sleep. UART0 Receive. Input/Output Definition
148
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Secondary General Purpose I/O 30361D
7.6
Secondary General Purpose I/O
The AU1500 processor contains two GPIO blocks (primary and secondary). This section describes the programming model of the secondary GPIO block which corresponds to signals labeled GPIO[200] through GPIO[215]. (For a description of the primary GPIO block refer to Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168 in the system control block description.) GPIO[200] is configured at reset to output a low logic level. This pin can be used as a PCI reset output (PCI_RSTO#) if it is required that the processor generate PCI reset. All other secondary GPIOs are configured as inputs on reset.
7.6.1
GPIO2 Programming Model
The secondary GPIO (GPIO2) logic block is controlled by a register block referenced from the base address described in Table 7-22.
Table 7-22. GPIO2 Register Base Addresses
Name gpio2_base Physical Base Address 0x0 1170 0000 KSEG1 Base Address 0xB170 0000
7.6.2
GPIO2 Registers
The secondary GPIO register block is shown in Table 7-23.
Table 7-23. GPIO2 Registers
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 Register Name gpio2_dir -- gpio2_output gpio2_pinstate gpio2_inten gpio2_enable Description GPIO2 Direction Reserved GPIO2 Data Output GPIO2 Pin State GPIO2 Interrupt Enable (for GPIO[215:208]) GPIO2 Enable
Note 1. See Table 7-22 for base address.
7.6.2.1 Direction Register The gpio2_dir register controls the direction of each GPIO2 signal. Note that this register only controls the output enable for the output buffer. Clearing a bit in this register disables the output for the corresponding pin making it possible to read an externally driven input. Output enable control can also be used to emulate an open drain driver.
gpio2_dir - Direction Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0000 3210 0 0 0 1
9 0
87 DIR 00
6 0
5 0
4 0
Bits 31:16 15:0
Name -- DIR
Description Reserved, should be cleared. Direction Control. Each bit controls the I/O direction of one GPIO signal in the secondary block. Bits 15:0 correspond to GPIO[215:200]. 0 1 Pin is an input (output disabled). Pin is an output.
R/W R R/W
Default 0 0x0001
Note that the GPIO[200] default direction is out because GPIO[200] is designed to act as a PCI reset output signal (PCI_RSTO#) if needed.
AMD AlchemyTM AU1500TM Processor Data Book
149
www..com
30361D Secondary General Purpose I/O
7.6.2.2 Data Output Register The gpio2_output register controls the output data for the secondary GPIOs. Data bits 15:0 are output to the corresponding GPIO when the enable bit is set for that bit during a write to this register. For example, to output a `1' on GPIO[200] and a `0' on GPIO[201] without changing the output of any other GPIOs, write the value 0x00030001 to gpio2_output.
gpio2_output - Data Output Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ENA Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Offset = 0x0008 3210 0 0 0 0
9 0
87 DATA 00
6 0
5 0
4 0
Bits 31:16
Name ENA[15:0]
Description Data Output Write Enable. ENA[15:0] corresponds to DATA[15:0]. Note that ENA is write-only and should be ignored on reads. 0 1 Disable modifications to corresponding bit in DATA[15:0]. Enable modifications to corresponding bit in DATA[15:0].
R/W W
Default 0x0001
15:0
DATA[15:0]
Output Data. DATA[15:0] corresponds to GPIO[215:200]. The DATA bit values are reflected in the corresponding GPIO output signal level. When modifying a bit in DATA[15:0], the corresponding bit in ENA[15:0] must be set to allow the write. This mechanism allows individual data bits to be modified without affecting DATA[15:0] as a whole.
R/W
0
7.6.2.3 Pin State Register The gpio2_pinstate register reflects the current state of the corresponding secondary GPIO pin.
gpio2_pinstate - Pin State Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x000C 3210 0 0 0 0
9 0
87 DATA 00
6 0
5 0
4 0
Bits 31:16 15:0
Name -- DATA
Description These bits are reserved and will be read 0. Current Pin State for GPIO[215:200]
R/W R R
Default 0 0
150
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Secondary General Purpose I/O 30361D
7.6.2.4 Interrupt Enable Register The gpio2_inten register contains bits which enable interrupts under certain operational conditions. Note that gpio2_inten applies only to interrupts on GPIO[215:208]. The GPIO[215:208] signals are OR'd together to create one interrupt source (source number 31 on interrupt controller 1), as shown in Figure 7-2. (The GPIO[207:200] signals can be used as independent interrupt sources.) See Section 6.0 "Interrupt Controller" on page 95 for more information on how to program interrupts.
GPIO[215] gpio2_inten[7] GPIO[214] gpio2_inten[6] Interrupt Source Number 31 (for Interrupt Controller 1) GPIO[208] gpio2_inten[0]
Figure 7-2. Logic for Interrupt Source Number 31 on Interrupt Controller 1
gpio2_inten - Interrupt Enable Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
Offset = 0x0010 43210 EN 00000
Bits 31:8 7:0
Name -- EN
Description Reserved, should be cleared. Interrupt enable bits [7:0] correspond to GPIO[215:208]. Setting a bit enables the signal's OR'd contribution to interrupt source number 31 (on interrupt controller 1).
R/W R R/W
Default 0 0
7.6.2.5 Enable Register The gpio2_enable register controls the clocks and reset to the secondary GPIO block.
gpio2_enable - Enable Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0014 3210 MR CE 00010 4
9 0
8 0
7 0
6 0
5 0
Bits 31:2 1 0
Name -- MR CE
Description Reserved, should be cleared. Module Reset. When this bit is set the module is held in reset. Clock Enable. When this bit is clear the module clocks are disabled.
R/W R R/W R/W
Default 0 1 0
AMD AlchemyTM AU1500TM Processor Data Book
151
www..com
30361D Secondary General Purpose I/O
152
AMD AlchemyTM AU1500TM Processor Data Book
www..com
System Control 30361D
8.0System Control
The AU1500 processor contains a robust system control strategy that includes the means to control the following: * Clocking (See Section 8.1 "Clocks" on page 154.) * Time of Year and Real Time Clock counters (See Section 8.2 "Time of Year Clock and Real Time Clock" on page 163.) * GPIO control (See Section 8.3 "Primary General Purpose I/O and Pin Functionality" on page 168.) * Power management (See Section 8.4 "Power Management" on page 172.) All registers in the system control block are located off of the base address shown in Table 8-1.
8
Table 8-1. System Control Block Base Address
Name sys_base Physical Base Address 0x0 1190 0000 KSEG1 Base Address 0xB190 0000
The registers in the system control block are affected differently by events such as power-on hardware reset, Sleep and runtime reset (see Section 9.0 "Power-up, Reset and Boot" on page 180 for a discussion on the different reset types). Each register is documented with how it will be affected by the different system states. Care should be taken by the system designer to observe what registers will and will not revert to defaults when the different events occur.
AMD AlchemyTM AU1500TM Processor Data Book
153
www..com
30361D Clocks
8.1
Clocks
The AU1500 processor supports two oscillator inputs: 12 MHz and 32.768 KHz. This section documents the clock domains driven directly and indirectly by the 12 MHz input. The 32.768 KHz clock input drives the two programmable counters intended for use as a real time clock (RTC) and time of year clock (TOY). The programmable counters are documented in Section 8.2 "Time of Year Clock and Real Time Clock" on page 163. (See Section 12.10 "Crystal Specifications" on page 234 for the specifications of both crystals.) The AU1500 processor contains two PLLs driven by the 12 MHz oscillator and a clocking block from which the following are derived: * CPU Clock * Core Cycle Counter register clocked by the CPU Clock * System Bus (SBUS) Clock * Peripheral Bus Clock * SDRAM Bus Clock * Programmable Clocks needed by certain peripherals * Programmable Clocks EXTCLK[1:0] for external use (provided on pins shared with the GPIO[3:2] signals) Figure 8-1 shows the basic clocking topology and the relationship between the CPU Clock, the SBUS clock and the Peripheral Clock. As shown, the SBUS frequency is derived by dividing the CPU Clock by the value SD programmed in the sys_powerctrl register. (See Section 8.4 "Power Management" on page 172 for the sys_powerctrl register definition.) The Peripheral Bus clock and the SDRAM bus are fixed at the SBUS frequency divided by 2. Figure 8-1 also shows the peripheral blocks driven by clock sources derived from the programmable clock generator logic (as described in Section 8.1.2 "Clock Generation" on page 155).
12.000 MHz
CPU_PLL
CPU Clock
/SD*
SBUS Clock
/2 /2
Peripheral Bus Clock SDRAM Bus Clock
AUX_PLL
CLOCK GENERATOR Auxiliary Clock PCI_CLKO USB Device USB Host EXTCLK0 EXTCLK1
*- SD is a programmable field in the sys_powerctrl register as described in Section 8.4.5 "Power Management Registers" on page 175. SD can be 2, 3, or 4.
Figure 8-1. Clocking Topology
154
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Clocks 30361D
8.1.1
Clock Register Descriptions
The clock manager registers and their associated offsets are listed in Table 8-2.
Table 8-2. Clock Generation Registers
Offset (Note 1) 0x0020 0x0024 0x0028 0x0060 0x0064 Register Name sys_freqctrl0 sys_freqctrl1 sys_clksrc sys_cpupll sys_auxpll Description Controls (source, enable, and divider) frequency generators 0, 1, and 2 Controls (source, enable, and divider) frequency generators 3, 4, and 5 Controls (source and divider) the derived clocks Changes CPU PLL frequency Changes Auxiliary PLL frequency Reset Type Hardware Hardware Hardware Hardware Hardware & Runtime
Note 1. See Table 8-1 on page 153 for base address.
8.1.2
Clock Generation
This section documents registers for the clock generation block which provides clocks to some peripheral devices and as well as two externally available clocks. The clock generation subsystem is split into two sets of distinct blocks which allows up to six distinct frequencies to drive up to six clock sources. Figure 8-2 on page 156 shows a logical representation of one of the six identical frequency generators and how the six frequency sources are mapped to one of the six identical internal clock sources. The names in the figure correspond to the bit names in the control registers. Figure 8-3 on page 156 shows a pictorial representation of the relationship between the frequency generator blocks to the clock source blocks. Each peripheral has clock restrictions as follows. If these restrictions are not met, the peripheral will not operate correctly. The USB Device Clock must be programmed to 48 MHz. The USB Host Clocks must be programmed to 48 MHz. The EXTCLK[1:0] clocks can be programmed for system use. Note that the EXTCLK[1:0] clocks have a maximum frequency rating of (Fmax / 16), where Fmax is the maximum frequency rating for the part. For example, for a 400 MHz part be sure the EXTCLK[1:0] clocks are programmed to run at no more than 25 MHz. (See also Section 12.9 "External Clock Specifications" on page 233.) Note also that the EXTCLK[1:0] clocks are multiplexed signals and require programming of the sys_pinfunc register (see Section 8.3.1.1 "Pin Function" on page 168) as follows: * EXTCLK0 shares a pin with GPIO[2]. If EXTCLK0 is to be used, sys_pinfunc[EX0] must be set to allow the clock to drive this pin. In addition, sys_pinfunc[CS] must be cleared. * EXTCLK1 shares a pin with GPIO[3]. If EXTCLK1 is to be used, sys_pinfunc[EX1] must be set to allow the clock to drive this pin.
AMD AlchemyTM AU1500TM Processor Data Book
155
www..com
30361D Clocks
Frequency Generator Block CPU Clock Auxiliary Clock 0
1
Divide = (FRDIVn + 1) * 2
FREQn
FSn Reserved Auxiliary Clock FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 0 1 2 3 4 5 6 7 MXX /4 /2
FEn Clock Source Block
0 0 1 DXX 1 CXX
Peripheral Clock Out
XX denotes the abbreviated peripheral name
Figure 8-2. Frequency Generator and Clock Source Block Diagram
CPU AUX CPU AUX CPU AUX CPU AUX CPU AUX CPU AUX
Freq. Gen. Block 0 Freq. Gen. Block 1 Freq. Gen. Block 2 Freq. Gen. Block 3 Freq. Gen. Block 4 Freq. Gen. Block 5
FREQ0 FREQ1 FREQ2
AUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 AUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 AUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 AUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 AUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5
USB Device Clock Source Block
USB Dev Clock
USB Host Clock Source Block
USB Host Clock
FREQ3 FREQ4 FREQ5
PCI Clock Output Source Block
PCI_CLKO
GPIO[2] Clock Source Block
EXTCLK0
GPIO[3] Clock Source Block
EXTCLK1
Figure 8-3. Frequency Generator and Clock Source Mapping
156
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Clocks 30361D
8.1.2.1 Frequency Control 0 This register controls the frequency generator block for output frequencies 0, 1, and 2. This register will reset to defaults only on a hardware reset. During a runtime reset and during Sleep this register will retain its value.
sys_freqctrl0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FRDIV2[7:0] FE2FS2 FRDIV1[7:0] FE1FS1 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0020 3210 FE0FS0 0000
8 0
7654 FRDIV0[7:0] 0000
Bits 31:30 29:22 21
Name -- FRDIV2 FE2
Description Reserved, should be cleared. Divider for Frequency Generator 2. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator Output Enable 2. 0 1 Disable output. Enable output.
R/W R R/W R/W
Default 0 0 0
20
FS2
Frequency Generator 2 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
19:12 11
FRDIV1 FE1
Divider for Frequency Generator 1. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator 1 Output Enable. 0 1 Disable output. Enable output .
R/W R/W
0 0
10
FS1
Frequency Generator 1 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
9:2 1
FRDIV0 FE0
Divider for Frequency Generator 0. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator 0 Output Enable. 0 1 Disable output. Enable output .
R/W R/W
0 0
0
FS0
Frequency Generator 0 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
AMD AlchemyTM AU1500TM Processor Data Book
157
www..com
30361D Clocks
8.1.2.2 Frequency Control 1 This register controls the frequency generator block for output frequencies 3, 4, and 5. This register will reset to defaults only on a hardware reset. During a runtime reset and during Sleep this register will retain its value.
sys_freqctrl1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FRDIV5[7:0] FE5FS5 FRDIV4[7:0] FE4FS4 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0024 3210 FE3FS3 0000
8 0
7654 FRDIV3[7:0] 0000
Bits 31:30 29:22 21
Name -- FRDIV5 FE5
Description Reserved, should be cleared. Divider for Frequency Generator 5. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator 5 Output Enable. 0 1 Disable output. Enable output .
R/W R R/W R/W
Default 0 0 0
20
FS5
Frequency Generator 5 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
19:12 11
FRDIV4 FE4
Divider for Frequency Generator 4. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator 4 Output Enable. 0 1 Disable output. Enable output .
R/W R/W
0 0
10
FS4
Frequency Generator 4 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
9:2 1
FRDIV3 FE3
Divider for Frequency Generator 3. The frequency divider is (FRDIV + 1) * 2, where FRDIV is the value programmed in this field. Frequency Generator 3 Output Enable. 0 1 Disable output. Enable output .
R/W R/W
0 0
0
FS3
Frequency Generator 3 Source. 0 1 CPU Core clock. Auxiliary clock.
R/W
0
158
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Clocks 30361D
8.1.2.3 Clock Source Control This register controls the clock source for all output clocks. This register will reset to defaults only on a hardware reset. During a runtime reset and during Sleep this register will retain its value.
sys_clksrc Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ME1[2:0] DE1 CG3 ME0[2:0] DE0 CE0 MPC[2:0] DPC CPC MUH[2:0] DUH CUH
9 0
8 0
7 0
6 0
5 0
4 0
Offset = 0x0028 3210 0 0 0 0
MUD[2:0]
DUD CUD
Def. 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits 31:30 29:27 26
Name -- ME1 DE1
Description Reserved, should be cleared. EXTCLK1 Clock Mux Input Select. See Table 8-3 on page 160. EXTCLK1 Clock Divider Select. 0 1 Divide by 4. Divide by 2.
Read/Write R R/W R/W
Default 0 000 0
25
CE1
EXTCLK1 Clock Select. 0 1 Clock is taken directly from mux. (The divider select bit DE1 has no effect.) Clock is taken from 2/4 divider.
R/W
0
24:22 21
ME0 DE0
EXTCLK0 Clock Mux Input Select. See Table 8-3 on page 160. EXTCLK0 Clock Divider Select. 0 1 Divide by 4. Divide by 2.
R/W R/W
000 0
20
CE0
EXTCLK0 Clock Select. 0 1 Clock is taken directly from mux. (The divider select bit DE0 has no effect.) Clock is taken from 2/4 divider.
R/W
0
19:17 16
MPC DPC
PCI Clock Mux Input Select. See Table 8-3 on page 160. PCI Clock Divider Select, 0 1 Divide by 4. Divide by 2.
R/W R/W
000 0
15
CPC
PCI Clock Select, 0 1 Clock is taken directly from mux. (The divider select bit DPC has no effect.) Clock is taken from 2/4 divider.
R/W
0
14:12 11
MUH DUH
USB Host Clock Mux Input Select. See Table 8-3 on page 160. USB Host Clock Divider Select. 0 1 Divide by 4. Divide by 2.
R/W R/W
000 0
10
CUH
USB Host Clock Select. 0 1 Clock is taken directly from mux. (The divider select bit DUH has no effect.) Clock is taken from 2/4 divider.
R/W
0
9:7 6
MUD DUD
USB Device Clock Mux Input Select. See Table 8-3 on page 160. USB Device Clock Divider Select. 0 1 Divide by 4. Divide by 2.
R/W R/W
000 0
5
CUD
USB Device Clock Select. 0 1 Clock is taken directly from mux. (The divider select bit DUD has no effect.) Clock is taken from 2/4 divider.
R/W
0
4:0
--
Reserved.
AMD AlchemyTM AU1500TM Processor Data Book
159
www..com
30361D Clocks
The specific values written to the 3-bit clock-mux-input-select fields are shown in Table 8-3. The FREQn selections come from the output of the corresponding frequency generators, as shown in Figure 8-2 on page 156.
Table 8-3. Clock Mux Input Select Values
Value 000 001 010 011 100 101 110 111 Meaning No clocking Auxiliary Clock FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5
8.1.3
PLL Control
There are two registers for controlling the two PLLs integrated into the AU1500 processor. Each PLL is independently programmable. Note that when programming the PLL control registers, the system designer must not violate the rated frequency limits of the AU1500 processor. Configuring the PLLs outside this frequency range causes undefined behavior. For higher frequencies the AU1500 processor core requires a higher core voltage (VDDI). Care should be taken that the system is providing the correct voltage for the operating frequency before changing the CPU clock. See Section 12.5 "DC Parameters" on page 218, for full information about the voltage/frequency requirements of the AU1500 processor. The Core Cycle Counter register located at CP0 register 9 can be used to count core cycles. Please see Section 2.7 "Coprocessor 0" on page 30, for more information. The two PLLs in the AU1500 processor drive the CPU clock and the auxiliary clock. The default PLL multiplier value is 16 for the CPU clock and 0 for the AUXPLL which has the following implications assuming a 12 MHz crystal on XTI12 and XTO12: * CPU Clock = 192 MHz * Auxiliary Clock = Disabled * SBUS Clock = 96 MHz (SD - SBUS divider - defaults to 2) * Peripheral Bus = 48 MHz * SDRAM Bus = 48 MHz. When modifying the CPU clock frequency approximately 20 s elapse while the CPU and bus clocks shut off and the CPU PLL locks to the new frequency. During this period instructions are not executed and interrupts are not serviced. Interrupts are serviced once execution begins again at the new frequency.
160
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Clocks 30361D
8.1.3.1 CPU PLL Control The CPU PLL control register (sys_cpupll) resets to its default value only for a hardware reset. That is, after Sleep, and during a runtime reset the CPU PLL retains its frequency. Note that when programming the CPU PLL control register the system designer must not violate the rated frequency limits of the AU1500 processor. Configuring the PLL outside this frequency range causes undefined behavior. This register is read/write, but the value read is valid only after initialization. After coming out of reset, hardware reset or Sleep, this register must first be written for the value read back to be valid. For this reason it is suggested that this register be initialized at boot time regardless if the value is changed from default. After writing to the sys_cpupll register, the system automatically halts for 20 s to allow for the PLL to relock and clocks to become stable.
sys_cpupll Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0
8 0
7 0
6 0
5 0
Offset = 0x0060 3210 PLL[5:0] 10000 4
Bits 31:6 5:0
Name -- PLL
Description Reserved, should be cleared. CPU PLL Multiplier. Determines the integer multiplier used to multiply the CPU PLL to generate the CPU clock. For example, with the default of 16 and a 12 MHz OSC frequency, the CPU clock frequency is 192 MHz. Note that PLL multiplier values that place the clock frequency outside of rated limits are invalid. 0-15: n-63: Reserved and undefined. Reserved and undefined. 16-(n-1): Valid PLL multiplier. Where n is the smallest PLL multiplier that would cause the CPU clock frequency to exceed the rated frequency limits of the part.
R/W R/W R/W
Default 0 0x10
AMD AlchemyTM AU1500TM Processor Data Book
161
www..com
30361D Clocks
8.1.3.2 Auxiliary PLL Control The auxiliary PLL control register (sys_auxpll) resets to its default value on hardware reset, after Sleep, and during a runtime reset. This register is read/write, but the value read is valid only after initialization. For this reason it is recommended that system software initialize this register at hardware reset, runtime reset and Sleep, even if programming its default value. Note that when programming the auxiliary PLL control register the system designer must not violate the rated frequency limits of the AU1500 processor. Configuring the PLL outside this frequency range causes undefined behavior. Unlike the sys_cpupll register, writing sys_auxpll does not cause the system to halt. As a consequence, clocks taken from the AUX PLL may be unstable for up to 20 s. To ensure stable clocks during AUX PLL lock time, the sys_cpupll register can be written with its current value to force the system to halt for 20 s.
sys_auxpll Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0064 3210 PLL[5:0] 00000 4
9 0
8 0
7 0
6 0
5 0
Bits 31:6 5:0
Name -- PLL
Description Reserved, should be cleared. Auxiliary PLL Multiplier. Determines the integer multiplier used to multiply the auxiliary PLL to generate the auxiliary clock. For example, with a value of 12 and a 12 MHz OSC frequency, the auxiliary clock frequency will be 144 MHz. Note that PLL multiplier values that place the clock frequency outside of rated limits are invalid. 0: 1-7: 8-(n-1): n-63: Disable the auxiliary PLL. Reserved and undefined. Valid PLL multiplier. Reserved and undefined.
R/W R/W R/W
Default 0 0x00
Where n is the smallest PLL multiplier that would cause the auxiliary clock frequency to exceed the rated frequency limits of the part.
8.1.4
Hardware Considerations
Note also that the EXTCLK[1:0] clocks are multiplexed signals and require programming of the sys_pinfunc register (see Section 8.3.1.1 "Pin Function" on page 168) as follows: When using the external clocks from the clock generation block, the sys_pinfunc register must be programmed such that GPIO[2] and/or GPIO[3] are configured to be driven by EXTCLK0 and/or EXTCLK1. Section 12.10 "Crystal Specifications" on page 234, define the crystal specifications.
8.1.5
Programming Considerations
When changing the CPU PLL value through the sys_cpupll register, the system automatically halts for 20 s to allow clocks to stabilize. During this time no interrupts are serviced, potentially affecting real-time systems. However, modifying the sys_auxpll register does not cause the system to halt, and therefore clocks taken from the AUX PLL may be unstable for up to 20 s. To ensure stable clocks while the AUX PLL locks, the sys_cpupll register can be written with its current value to force the system to halt for 20 s.
162
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Time of Year Clock and Real Time Clock 30361D
8.2
Time of Year Clock and Real Time Clock
The AU1500 processor contains two programmable counters designed for use as a time of year clock (TOY) and real time clock (RTC). Because the TOY continues counting through Sleep, a TOY counter match can be used as a wake-up source. The RTC, however, will power down in Sleep mode. Note that both the TOY and RTC counters are driven by the 32.768 KHz clock input. The clock input source can be a crystal or external clock. (See Section 12.10 "Crystal Specifications" on page 234 for crystal details.) Each programmable counter employs a register to initialize the counter or load a new value, a trim divider to adjust the incoming 32.768 KHz clock, and three match registers which have associated interrupts that trigger on a match. Each counter is also able to generate an interrupt on every tick. All interrupts are maintained through the interrupt controller. Both programmable counters share a status register. Figure 8-4 shows the functional block diagram of both the TOY and the RTC. The registers used to implement the block, including the counter control register (sys_cntrctrl), are described in the following section.
Divide = TRIM + 1
0 TOY Counter
1
Interrupt
Comparators
Match0
Interrupt Interrupt Interrupt
sys_cntrctrl[BTT] GPIO[8] 32.768 KHz sys_cntrctrl[EO] sys_cntrctrl[BP] Divide = TRIM + 1 0
1
Match1
0
Match2
RTC Counter
1
Interrupt
Comparators
Match0
Interrupt Interrupt Interrupt
sys_cntrctrl[BRT]
Match1
Match2
Figure 8-4. TOY and RTC Block Diagram
AMD AlchemyTM AU1500TM Processor Data Book
163
www..com
30361D Time of Year Clock and Real Time Clock
8.2.1
Time of Year Clock and Real Time Clock Registers
Each counter operates identically with the only difference being that the TOY continues counting through Sleep and the RTC does not. The programmable counter control registers and their associated offsets are listed in Table 8-4. When functionality is identical for registers in the different programmable counters, only one general register description is presented with offsets pointing to the specific registers.
Table 8-4. Programmable Counter Registers
Offset (Note 1) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 Register Name sys_toytrim sys_toywrite sys_toymatch0 sys_toymatch1 sys_toymatch2 sys_cntrctrl sys_toyread sys_rtctrim sys_rtcwrite sys_rtcmatch0 sys_rtcmatch1 sys_rtcmatch2 sys_rtcread Description Trim value for 32.768 KHz clock source for TOY TOY counter value is written through this register. TOY match 0 value for interrupt generation. TOY match 1 value for interrupt generation. TOY match 2 value for interrupt generation. Control register for TOY and RTC. TOY counter value is read from this register. Trim value for 32.768 KHz clock source for RTC. RTC counter value is written through this register. RTC match 0 value for interrupt generation. RTC match 1 value for interrupt generation. RTC match 2 value for interrupt generation. RTC counter value is read from this register. Reset Type Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware
Note 1. See Table 8-1 on page 153 for base address.
8.2.1.1 Trim Register The TOY trim write status bit (sys_cntrctrl[TTS]) must be clear before writing sys_toytrim. It is set upon writing this register and is cleared by hardware when the write takes effect. The RTC trim write status bit (sys_cntrctrl[RTS]) must be clear before writing sys_rtctrim. It is set upon writing this register and is cleared by hardware when the write takes effect. This register is unpredictable at power on. During a runtime reset and during Sleep this register retains its value.
sys_toytrim - TOY Trim sys_rtctrim - RTC Trim Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X Offset = 0x0000 Offset = 0x0044 43210 X X X X X
876 TRIM[15:0] XXXX
9
5 X
Bits 31:16 15:0
Name -- TRIM
Description Reserved, should be cleared. Divide value for 32.768 KHz input. Divide = TRIM + 1.
R/W R R/W
Default 0 UNPRED
164
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Time of Year Clock and Real Time Clock 30361D
8.2.1.2 Counter Write The TOY value write status bit (sys_cntrctrl[TS]) must be clear before writing sys_toywrite. It is set upon writing this register and is cleared by hardware when the write takes effect. The RTC value write status bit (sys_cntrctrl[RS]) must be clear before writing sys_rtcwrite. It is set upon writing this register and is cleared by hardware when the write takes effect. This register is unpredictable at power on. During a runtime reset and during Sleep this register retains its value.
sys_toywrite - TOY counter value write sys_rtcwrite - RTC counter value write Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 COUNT[31:0] Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0004 Offset = 0x0048 43210 X X X X X
8 X
7 X
6 X
5 X
Bits 31:0
Name COUNT
Description Counter Write. The respective counter will be updated with the value written to this register at the next trimmed clock.
R/W W
Default UNPRED
8.2.1.3 Match Registers The corresponding write status bit (sys_cntrctrl[TMn] or sys_cntrctrl[RMn]) must be clear before writing the below registers. It is set upon writing the register and is cleared by hardware when the write takes effect. Each match register is capable of causing an interrupt as shown in Section 6.0 "Interrupt Controller" on page 95. The sys_toymatch2 can be used to wake up from Sleep; see Section 8.4.5.2 "Wakeup Source Mask Register" on page 176. See also Section 8.2.2 "Programming Considerations" on page 167. These registers are unpredictable at power on. During a runtime reset and during Sleep these registers retain their value.
sys_toymatch0 - TOY Match 0 sys_toymatch1 - TOY Match 1 sys_toymatch2 - TOY Match 2 sys_rtcmatch0 - RTC Match 0 sys_rtcmatch1 - RTC Match 1 sys_rtcmatch2 - RTC Match 2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 MATCH[31:0] Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0008 Offset = 0x000C Offset = 0x0010 Offset = 0x004C Offset = 0x0050 Offset = 0x0054 43210 X X X X X
8 X
7 X
6 X
5 X
Bits 31:0
Name MATCH
Description A match with the counter and the value in this register causes an interrupt.
R/W R/W
Default UNPRED
8.2.1.4 TOY and RTC Counter Control The TOY and RTC counter control register (sys_cntrctrl) contains control bits and status bits to configure and control both programmable counters. Write Status Bits: These bits indicate the status of the latest update to the respective register/field. When the corresponding register/field is written, this bit is set indicating that there is a write pending. When this bit is cleared the write has taken place. Software should poll the correct bit and insure that it is 0 before updating the respective register/field. This register resets to default values only on a hardware reset. During a runtime reset and during Sleep this register retains its value.
sys_cntrctrl Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RTSRM2RM1RM0 RS BP BRT BTT
9 0
8 0
7 0
6 0
5 X
4 0
Offset = 0x0014 3210 0 0 0 0
EO CCS
32S TTS TM2 TM1 TM0 TS
Def. 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AMD AlchemyTM AU1500TM Processor Data Book
165
www..com
30361D Time of Year Clock and Real Time Clock
Bits 31:21 20 19 18 17 16 15 14
Name -- RTS RM2 RM1 RM0 RS -- BP
Description Reserved, should be cleared. sys_rtctrim Write status. sys_rtcmatch2 write status. sys_rtcmatch1 write status. sys_rtcmatch0 write status. sys_rtcwrite write status 0 1 No write is pending. It is safe to write to the register. A write is pending. Do not write to the register.
R/W R R R R R R R R/W
Default 0 0 0 0 0 R 0 0
Reserved, should be cleared. Bypass the 32.768 KHz OSC 0 1 Select Oscillator Input (XTI32, XTO32). GPIO[8] drives the counters. This is a test mode where GPIO[8] can drive the counters from an external source or through software using the GPIO controller.
13 12
-- BRT
Reserved, should be cleared. Bypass RTC Trim. 0 1 Normal operation. The RTC is driven directly by the 32.768 KHz clock, bypassing the trim.
R/W R/W
0 0
11 10
-- BTT
Reserved, should be cleared. Bypass TOY Trim. 0 1 Normal operation. The TOY is driven directly by the 32.768 KHz clock, bypassing the trim.
R/W R/W
0 0
9 8
-- EO
Reserved, should be cleared. Enable 32.768 KHz Oscillator. Enables the clock for the RTC/TOY block. 0 1 Disable the clock. Enable the clock.
R R/W
0 0
Regardless of the clock source (crystal or overdriven clock through XTI32/ XTO32, or bypass through GPIO[8]), the EO bit must be set to enable the RTC/TOY counters. After enabling the clock by setting EO, poll the oscillator status bit (32S) until it returns a `1'. Once 32S is set, wait an additional one second to allow for frequency stabilization within the block before accessing other RTC/TOY registers (not including sys_cntrctrl). Note: If the oscillator is being overdriven or bypassed through GPIO[8], be sure to set EO only after a stable clock is being driven into the part. R R R 0 0 UNPRED
7 6 5
CCS -- 32S
sys_cntrcntrl write status Reserved, should be cleared. 32.768 KHz Oscillator Status. Detects two consecutive 32 KHz cycles from the clock source for the RTC/TOY block. 0 1 Clock is not running. Clock is running. Be sure to wait 1 second after 32S is set to allow for frequency stabilization within the block before accessing RTC/TOY registers.
Note:
4 3 2 1 0
TTS TM2 TM1 TM0 TS
sys_toytrim write status. sys_toymatch2 write status. sys_toymatch1 write status. sys_toymatch0 write status. sys_toywrite write status 0 1 No write is pending. It is safe to write to the register. A write is pending. Do not write to the register.
R R R R R
0 0 0 0 0
166
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Time of Year Clock and Real Time Clock 30361D
8.2.2
Programming Considerations
To change the values of the counter and match registers, software must poll the state of the corresponding status bit in sys_cntrctrl. When the corresponding write status bit (sys_cntrctrl[TTS,TMn,TS] or sys_cntrctrl[RTS,RMn,RS]) is 0 it is okay to write a new value. Once the new value is written to the register the status bit will change to a 1. When the write status bit is 1 the new value is being updated in supporting hardware. When the write status changes to a 0 then the new value is active in the device.
AMD AlchemyTM AU1500TM Processor Data Book
167
www..com
30361D Primary General Purpose I/O and Pin Functionality
8.3
Primary General Purpose I/O and Pin Functionality
The AU1500 processor contains two separate GPIO blocks (primary and secondary). This section covers the programming model for the primary general purpose I/O (GPIO) signals. The AU1500 processor supports 39 GPIOs, 23 of which are controlled by the primary GPIO block. For a description of the programming model for the secondary GPIO block see Section 7.6 "Secondary General Purpose I/O" on page 149. This section also documents how to change the functionality of multiplexed pins. These pins can function at the system level as a GPIO signal, or they can be assigned a signal function dedicated to an integrated peripheral device. Each GPIO can be configured as either an input or an output. The GPIO ports also can be connected to the internal interrupt controllers to generate an interrupt from input signals. See Section 6.0 "Interrupt Controller" on page 95 for information on interrupts.
8.3.1
Pin Functionality
To maximize the functionality of the AU1500 processor, many of the pins have multiple uses. Note that if a pin is programmed for a certain use, any other functionality associated with that pin can not be utilized at the same time. In other words, a pin can not be used as a GPIO at the same time it is assigned to a peripheral device. (For reference,Figure 11-1 on page 201 shows a block diagram of all external signals. Signals that are multiplexed on one pin will show the shared function in parentheses.) 8.3.1.1 Pin Function This register resets to its default state at hardware reset, runtime reset and Sleep.
sys_pinfunc Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CS USB U3
9 0
8 0
7
UR3
6 0
5 1
4 1
Offset = 0x002C 3210 1 1 0 1
U1 SRC EX1 EX0
NI2 U0
Def. 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
Bits 31:17 16
Name -- CS
Description These bits are reserved and should be cleared. Clock Select. Applies only when EX0 = 1. 0 1 EXTCLK0 will drive pin. 32 KHz OSC clock will drive pin.
R/W R R/W
Default all 0s 0
15
USB
USB Functionality 0 1 USBDP and USBDM will drive pins (pins are connected to USB device module). USBH0P and USBH0M will drive pins (pins are connected to USB host port 0).
R/W
0
14
U3
UART3/GPIO[23]. 0 1 U3TXD drives pin. Pin is configured for GPIO[23].
R/W
1
13:12 11
-- SRC
These bits are reserved and should be written as 0b11. GPIO[6]/SMROMCKE. 0 1 Pin is configured for GPIO[6]. SMROMCKE drives pin.
R/W R/W
11 0
10
EX1
GPIO[3]/EXTCLK1. 0 1 Pin is configured for GPIO[3]. EXTCLK1 will drive pin.
R/W
0
9
EX0
GPIO[2] / (EXTCLK0 or 32 KHz OSC). 0 1 Pin is configured for GPIO[2]. Pin is configured for EXTCLK0 or 32 KHz OSC. CS (bit 16) selects whether EXTCLK0 or the 32 KHz OSC drives the pin.
R/W
0
8
--
This bit is reserved and should be written as 0.
R/W
0
168
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Primary General Purpose I/O and Pin Functionality 30361D
Bits 7
Name UR3
Description GPIO[14:9]/UART3. 0 1 Pins are configured as GPIO[14:9]. Pins are configured for optional UART3 flow control. U3DTR#, U3RTS#, U3RI#, U3DCD#, U3DSR#, and U3CTS# will drive pins.
R/W R/W
Default 0
System Note: For systems that use the UART3 interface but do not use the optional modem control signals (UR3=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input. 6:5 4 -- NI2 These bits are reserved and should be written as 0b01. MAC1/GPIO[28:24]. 0 1 3 U0 0 1 2:0 -- Pins are configured as Ethernet port 1. N1TXD[3:0], and N1TXEN will drive port. Pins are configured as GPIO[28:24]. R/W 1 Pin is configured for U0TXD (necessary for UART0 operation). Pin is configured as GPIO[20]. R/W 101 R/W R/W 01 1
UART0/GPIO[20].
These bits are reserved and should be written as 0b101.
8.3.2
Primary GPIO Control Registers
The primary GPIOs on the AU1500 processor have been designed to simplify the GPIO control process by removing the need for a semaphore to control access to the registers. This is because there is no need to read, modify, write, as there are separate registers for setting and clearing a bit. In this way a function can freely manipulate its associated GPIOs without interfering with other functions. Figure 8-5 shows the logical implementation of each GPIO. The names represent bit n of the corresponding register which affect GPIO[n].
sys_outputrd[n]
S-R sys_outputset[n] S R sys_outputclr[n] sys_pinstaterd[n] Pin
sys_trioutrd[n] R sys_trioutclr[n] S S-R
Figure 8-5. GPIO Logic Diagram
AMD AlchemyTM AU1500TM Processor Data Book
169
www..com
30361D Primary General Purpose I/O and Pin Functionality
The following table shows the GPIO control registers and the associated offsets from sys_base. Certain registers share offsets and have different functionality depending on whether the access is a read or a write. The register descriptions detail the functionality of each register. Bit n of a particular register should be associated with GPIO[n] for all registers except sys_pininputen.
Table 8-5. GPIO Control Registers
Offset (Note 1) 0x0100 0x0100 Register Name sys_trioutrd sys_trioutclr Register Description The TRI-STATE/Output state register shows the current state of the GPIO. 0 1 GPIO[n] is in TRI-STATE. To TRI-STATE GPIO[n] set the corresponding bit in the sys_trioutclr register. Output is enabled. To enable GPIO[n] as an output programming GPIO[n] as a 0 or 1 using the sys_outputclr[n] or sys_outputset[n] registers. Default 0x00000000 (all GPIOs are TRI-STATED)
If the pin is not an output it should be in TRI-STATE. 0x0108 0x0108 0x010C sys_outputrd sys_outputset sys_outputclr Controls the state of the GPIO[n] as an output. 0 1 To output a low level, set sys_outputclr[n]. To output a high level, set sys_outputset[n]. UNPRED
Programming a bit value in the output register brings the pin out of TRI-STATE mode and enables the output. 0x0110 0x0110 sys_pinstaterd sys_pininputen Allows the pin state to be read when an input. This register will also give the output state. Any write to this register allows GPIO[31:0] to be used as inputs. This register must be written before any GPIO can be used as an input, an interrupt source, or for use as a wake up source. UNPRED UNPRED
Note 1. See Table 8-1 on page 153 for base address.
8.3.2.1 GPIO Control Registers Each GPIO control register is 32 bits wide with bit n in each register affecting GPIO[n]. These registers will reset to defaults only on a hardware reset. During a runtime reset and during Sleep this register will retain its value. See Table 8-5 for the default values at hardware reset.
*rd *set *clr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FUNC[31:0]
9
8
7
6
5
4
3
2
1
0
Bits 31:0
Name FUNC[n]
Description The function of each register is given in the previous table. FUNC[n] controls the functionality of GPIO[n].
Read/Write *_read - read only *_set - write only *_clear - write only See the following text.
Default 0
170
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Primary General Purpose I/O and Pin Functionality 30361D
Certain registers in the list have the same offset but offer different functionality depending on whether a read or a write is being performed. Registers ending in *rd, *set and *clr have the following functionality: * *rd registers are read only registers will read back the current value of the register. * *set registers are write only registers and will set to 1 all bits that are written 1. Writing a value of 0 will have no impact on the corresponding bit. * *clr registers are write only registers and will clear to zero all bits that are written 1. Writing a value of 0 will have no impact on the corresponding bit. 8.3.2.2 GPIO Input Enable The sys_pininputen is a 32-bit, write-only register. When this register is written, the input functionality of all GPIOs is enabled. This register enables GPIOs for use as an input but does not explicitly configure all GPIOs as inputs. The value of the GPIO control registers and the pin function register will define the state of each GPIO. GPIOs cannot be used as inputs until this register is written. This write is required only once per hardware reset (i.e., Sleep and a runtime reset will not require another write to this register).
sys_pininputen Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0110 3210 EN XXXXX 4
9 X
8 X
7 X
6 X
5 X
Bits 31:1 0
Name -- EN
Description Reserved, should be cleared. A write to this bit (0 or 1) enables all GPIOs to be used as inputs.
R/W W W
Default N/A N/A
8.3.3
Hardware Considerations
The system pin function register (sys_pinfunc) controls the functionality of many GPIO/peripheral pins. If a pin is programmed for a certain functionality, all other functionality associated with that pin is disabled. For example, if sys_pinfunc[U3] is cleared configuring the pin as U3TXD, GPIO[23] can not be used as a GPIO nor can the GPIO be configured as an interrupt. Conversely if sys_pinfunc[U3] is set configuring the pin as GPIO[23], U3TXD (and thus the UART3 interface) is not usable. GPIO[23] can be used as a GPIO and to generate interrupts.
8.3.4
Using GPIO for External DMA Requests
See Section 5.2 "Using GPIO as External DMA Requests (DMA_REQn)" on page 92 for information.
AMD AlchemyTM AU1500TM Processor Data Book
171
www..com
30361D Power Management
8.4
Power Management
The AU1500 processor contains a robust power management scheme allowing multiple levels of power conservation to enable the system designer options depending on whether power conservation or system responsiveness is more critical. In the AU1500 processor, power management can be broken into three different areas: * CPU * Peripherals * Device The lowest power state consists of putting the entire device into a Sleep state. The CPU also supports two Idle states that differ as to whether bus snooping is supported. In addition each peripheral can have its clocks disabled when not in use thus significantly reducing the power draw by those blocks not in use. The flow chart in Figure 8-6 shows the different stages of power management for the CPU (IDLE0,1) and the device (SLEEP) and how each state is entered and left. Note that any interrupt can be used to bring the CPU out of either Idle state while only a GPIO[7:0] or sys_toymatch2 interrupt can be enabled (in sys_wakemsk) to bring the device out of Sleep.
Normal Operation
Prepare to Sleep
- Flush Cache - SDRAM Sleep - Turn off Peripherals - Enable Sleep Power - Set Sleep bit
Execute WAIT0
Execute WAIT1
IDLE0 (Snoop)
IDLE1 (No Snoop)
SLEEP Wakeup Enabled Interrupt TOY Match or GPIO[7:0] Interrupt Wakeup Enabled Interrupt
Yes
Yes
Yes
REBOOT
Figure 8-6. Sleep and Idle Flow Diagram 8.4.1 CPU Power Management - Idle
The CPU can be put into two different low-power Idle modes (IDLE0 and IDLE1) by using the wait instruction: * In the IDLE0 state the CPU snoops the bus and cache coherency is maintained. * In the IDLE1 state the CPU does not snoop the bus and cache coherency is lost. The wait instruction and at least four instructions following it must be in the cache for the wait to occur. See Section 2.6.3 "WAIT Instruction" on page 29 for more information. At all times the MMU, data cache, execution and multiply-and-accumulate blocks are placed in a low power state if they are not being used.
172 AMD AlchemyTM AU1500TM Processor Data Book
www..com
Power Management 30361D
8.4.2
Returning from Idle
The processor wakes from the Idle state (IDLE0 or IDLE1) upon receiving an interrupt. The time required for the processor core to return to normal execution is as follows: * Five to ten CPU clocks are needed to restart clocks to the CPU. * It takes an additional ten CPU clocks for the core to recognize the interrupt and begin fetching the interrupt service routine. Therefore, a maximum of 20 CPU clocks are required to resume normal instruction pipeline execution. If the interrupt service routine is in the instruction cache, the instruction returns immediately; otherwise, there is an additional delay while fetching the instruction from memory.
8.4.3
Peripheral Power Management
Peripheral power management is handled through clock management and disabling of unused peripherals. Table 8-6 lists the peripherals and their related power management registers. The actual register descriptions should be referred to for programming details. Note that when separate reset/peripheral enable and clock-enable bits are provided, the reset must be applied first, and then the clocks should be disabled. This will simplify programming, as the suggested bring up sequence is typically to first enable clocks and then subsequently to bring the peripheral out of reset.
Table 8-6. Peripheral Power Management
Power Management Register usbh_enable
Peripheral USB Host
Power Management Strategy When the USB host is not in use the E bit can be cleared to disable the host. The CE bit should also be cleared to disable clocks to the block. When the USB device is not in use the E bit can be cleared to disable the host. The CE bit should also be cleared to disable clocks to the block. When either block is not being used, the respective E[2:0] bits should be cleared to disable the MAC, and the CE bit should be cleared to gate clocks to the MAC. When a UART is not being used, the E bit should be cleared to hold the part in reset and the CE bit should be cleared to disable clocks to the block. Although there is not a specific low-power configuration for the primary GPIOs, tristating the unused GPIOs minimizes their power usage. If no GPIO2 signals are being used, the GPIO2 module reset (MR) bit should be set to place the module in reset. Also, clear the CE bit to disable clocks to the block. (By default, the GPIO2 module is disabled coming out of reset.) If both the TOY and RTC are not being used, then disable the oscillator. If the AC97 block is not in use, the D bit should be used to disable the module and the CE bit should be disabled to gate clocks from the block.
USB Device
usbd_enable
Ethernet MACn
macen_macn
UARTn
uartn_enable
Primary General Purpose I/O (GPIO) Controller Secondary General Purpose I/O (GPIO2) Controller Programmable Counters (TOY and RTC) AC97 Controller
sys_trioutclr
gpio2_enable
sys_cntrctrl
ac97_enable
AMD AlchemyTM AU1500TM Processor Data Book
173
www..com
30361D Power Management
8.4.4
Device Power Management - Sleep
The Sleep state of the AU1500 processor puts the entire device into a low-power state. Sleep is the lowest power state of the part and requires a complete system initialization on wakeup. There are multiple steps to take when going into Sleep and waking up to insure data integrity. During this state all registers values outside the system control block are lost and cache coherency is not maintained. The programmable counter 0 (intended for TOY) continues clocking and remains functional during Sleep. However, the programmable counter 1, as well as other clocks throughout the AU1500, are disabled during Sleep. When coming out of Sleep there is a programmable delay defined by sys_powerctrl[VPUT]. This is the time that the system designer has to ensure VDDI is stable from the rising edge of PWR_EN. To enter Sleep the following steps should be taken. This code should be run from Flash, or conversely the system programmer should guarantee that this code will run from cache because after SDRAM is put into auto-refresh mode, memory accesses will no longer work. 1) 2) 3) 4) Enable Sleep Power by writing to the sys_slppwr register. Turn off all peripherals. (Explicitly turning off all peripherals in use ensures a graceful transition to Sleep mode.) Push dirty data out of the cache. (During Sleep cached data is lost.) If SDRAM contents are to be kept through Sleep, SDRAM should be put into auto-refresh mode. See Section 3.1 "SDRAM Memory Controller" on page 44 for more information. If SDRAM is not needed to be maintained through Sleep, disable the SDRAM. 5) 6) 7) 8) 9) If using one of GPIO[7:0] as a wakeup source, sys_pininputen must be written to enable the GPIO as an input if this has not already been done at system startup. The sys_wakemsk register should be set with the appropriate value according to what signal(s) should wake the processor. The sys_wakesrc register should be written to explicitly clear any pending wake interrupts. Enable Sleep by writing to the sys_sleep register. This step puts the system to Sleep. As the system enters Sleep mode, the PWR_EN signal is negated. This can be used to disable VDDI if needed.
When the processor takes a Sleep interrupt to wake up, the following steps should be taken: 1) 2) 3) After the Sleep interrupt is taken, the PWR_EN signal is asserted by hardware. Within the time indicated by sys_powerctrl[VPUT], the system must ensure that VDDI is stable. The processor will then boot from physical address 0x0 1FC0 0000 as normal. If Sleep is to be used by the system and a different flow should be followed when coming out of Sleep the sys_wakesrc should be read to determine if the processor is coming out of Sleep and what caused the wakeup. The system should then write the sys_wakesrc register to clear this information. The processor will need to perform complete system initialization. All registers except those described as otherwise in the System Control Block will be at their default values.
4)
8.4.4.1 Sleep Sequence and Timing As the processor enters Sleep mode, the system designer has the option of disabling VDDI to conserve power. The PWR_EN signal defines the Sleep window. Figure 8-7 shows the Sleep sequence.
VDDI
VPUT
PWR_EN
Figure 8-7. Sleep Sequence
The system designer must ensure VDDI is stable from the rising edge of PWR_EN within the time period as programmed in sys_powerctrl[VPUT]. Note that VDDXOK (not shown) remains asserted during the Sleep sequence.
174
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Power Management 30361D
8.4.5
Power Management Registers
The power management registers and their associated offsets are listed in Table 8-7. These registers are located off of the base shown in Table 8-1 "System Control Block Base Address" on page 153.
Table 8-7. Power Management Registers
Offset (Note 1) 0x0018 0x001C 0x0034 0x0038 0x003C 0x005C 0x0078 0x007C Register Name sys_scratch0 sys_scratch1 sys_wakemsk sys_endian sys_powerctrl sys_wakesrc sys_slppwr sys_sleep Description User-defined register that retains its value through Sleep. User-defined register that retains its value through Sleep. Sets which GPIO or whether TOY match can cause Sleep wakeup. Sets Big or Little Endian. Sets System Bus (SBUS) divider and power-up time. Gives source of Sleep wakeup. Initiates power state for Sleep mode. Initiates Sleep mode. Reset Type Hardware Hardware Hardware Hardware & Runtime Mixed - See Register Description Hardware Hardware Hardware
Note 1. See Table 8-1 on page 153 for base address.
8.4.5.1 Scratch Registers The scratch registers keep their values through Sleep and runtime resets. These registers allow the system programmer to save user-defined state information or a pointer to a context so that the previous context can be restored when coming out of Sleep, if needed. Note that the scratch registers have unpredictable default values after a hardware reset.
sys_scratch0 sys_scratch1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SCRATCH[31:0] Def. X X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0018 Offset = 0x001C 43210 X X X X X
8 X
7 X
6 X
5 X
Bits 31:0
Name SCRATCH
Description User-defined information.
R/W R/W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
175
www..com
30361D Power Management
8.4.5.2 Wakeup Source Mask Register For each individual bit that is set, the corresponding signal or event (for the case of the TOY match) can be used to cause a Sleep wakeup. A high level on the enabled GPIO will cause the interrupt to trigger. This register will reset to defaults only on a hardware reset. During a runtime reset and during Sleep this register retains its value.
sys_wakemsk Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0034 43210 GPIO[7:0] 000000 5
87 M2 000
9
6 0
Bits 31:9 8
Name -- M2
Description Reserved, should be cleared. Setting this bit enables the programmable TOY Counter Match Register 2 (sys_toymatch2) to cause a wakeup interrupt. See Section 8.2.1.3 "Match Registers" on page 165. Setting bit n causes GPIO[n] to cause a Sleep wakeup.
R/W R R/W
Default 0 0
7:0
GPIO[7:0]
R/W
0
8.4.5.3 Endianness Register To change the endianness of the AU1500 processor is a three step process as follows: 1) 2) 3) 4) Program the endianness bit in the system endianness register (sys_endian[EN]). Read the sys_endian register. (This is required to ensure the final write to the CP0 register will update the endian value.) Read the CP0 register Config0. (See Section 2.7.15 "Configuration Register 0 (CP0 Register 16, Select 0)" on page 36.) Write the value read back into the CP0 Config0 register. The act of writing the CP0 register will put the processor into the endian state as programmed in sys_endian[EN].
This register as well as the processor endianness will reset to big endian after a hardware reset, runtime reset and after Sleep.
sys_endian Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. X X X X X X X X X X X X X X X X X X X X X X Offset = 0x0038 3210 EN XXXX0 4
9 X
8 X
7 X
6 X
5 X
Bits 31:1 0
Name -- EN
Description Reserved, should be cleared. Endianness. 0 1 Big Endian. Little Endian.
R/W R R/W
Default UNPRED 0
176
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Power Management 30361D
8.4.5.4 Power Control Register Bits[6:5] of this register are reset to default values for a hardware reset, runtime reset and after Sleep. Bits[4:0] of this register reset to default values only on a hardware reset. During a runtime reset and during Sleep these bits retain their values.
sys_powerctrl Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x003C 3210 VPUT SD 0000
9 0
8 0
7 0
654 SI SB 000
Bits 31:7 6
Name -- SI
Description Reserved, should be cleared. Idle State SBUS Clock Divider Enable 0 1 The Idle state SBUS clock divider is disabled. Enable the SBUS clock to be divided by an additional factor of 2 when the processor is in an IDLE state (taken through the WAIT instruction). All peripheral bus clocks (such as the SDRAM and UART controllers) will be internally compensated with no programmer intervention required. SD must be programmed to 00 (divide by two) when SI is set.
R/W R R/W
Default 0 0
Note: 5 SB 0 1
SBUS Clock Divider Enable The SBUS clock divider is disabled. Enable the SBUS clock to be divided by an additional factor of 2 when there is no bus activity. All clocks derived from the peripheral bus clock (such as the SDRAM and UART controllers) will be internally compensated with no programmer intervention required. SD must be programmed to 00 (divide by two) when SB is set.
R/W
0
Note: 4 3:2 -- VPUT
Reserved, should be cleared. VDDI Power-up Time. 00 01 10 11 20 ms 5 ms 100 ms 2 s
R R/W
0 Hardware Reset 00
1:0
SD
SBUS Clock Divider. 00 01 10 11 2 3 4 Reserved
R/W
Hardware Reset 00
AMD AlchemyTM AU1500TM Processor Data Book
177
www..com
30361D Power Management
8.4.5.5 Wakeup Cause Register Before setting the Sleep bit this register should be cleared. This register will retain pending interrupts according to the setting in the sys_wakemsk register even if those events did not occur during Sleep. In other words if a GPIO's functionality is multiplexed between multiple functions, a high level could cause the associated sys_wakesrc bit to be set even if the action did not occur during Sleep. The bits in this register must be explicitly cleared as they will hold their values through Sleep and a runtime reset. All bits in this register are set by hardware and cleared by any write to this register.
sys_wakesrc Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
M2 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
9 0
8 0
7 0
6 0
5 0
4 0
Offset = 0x005C 3210
SW IP
Def. 0
0
0
0
0
0 Rs 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Rs
Bits 31:25 24
Name -- M2
Description Reserved, should be cleared. Programmable TOY Match 2 caused wakeup from Sleep. Set by hardware on Sleep wakeup due to TOY match. Cleared by hardware on VDDXOK assertion. This bit must be explicitly cleared by software (any write) because it holds its value through Sleep and runtime reset.
R/W R/W R/W
Default 0 0
23 22 21 20 19 18 17 16 15:2 1
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 -- SW
GPIO[n] caused wakeup from Sleep. Set by hardware on Sleep wakeup due to GPIO[n]. This bit must be explicitly cleared by software (any write) because it holds its value through Sleep and runtime reset.
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0
Reserved, should be cleared. Sleep Wakeup. This bit is set by hardware on a Sleep wakeup and cleared by software by a write to this register. A runtime reset can be detected if both SW and IP are 0 at boot. This bit must be explicitly cleared by software (any write) because it holds its value through Sleep and runtime reset.
R/W R/W
0
IP
Initial Power-up. This bit is set by hardware on a hardware reset and cleared by software by a write to this register. A runtime reset can be detected if both SW and IP are 0 at boot. This bit must be explicitly cleared by software (any write) because it holds its value through Sleep and runtime reset.
R/W
1
178
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Power Management 30361D
8.4.5.6
Sleep Power Register
8 X 7 X 6 X 5 X 4 X Offset = 0x0078 3210 X X X X
sys_slppwr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SP Def. X X X X X X X X X X X X X X X X X X X X X X X
Bits 31:0
Name SP
Description A write to this register prepares the internal power supply for going to Sleep.
R/W W
Default UNPRED
8.4.5.7
Sleep Register
8 X 7 X 6 X 5 X 4 X Offset = 0x007C 3210 X X X X
sys_sleep Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SL Def. X X X X X X X X X X X X X X X X X X X X X X X
Bits 31:0
Name SL
Description A write to this register puts system to Sleep.
R/W W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
179
www..com
Power-up, Reset and Boot 30361D
9.0Power-up, Reset and Boot
This section presents the power-up, hardware reset and runtime reset sequence for the AU1500 processor. In addition the boot vector is described.
9
9.1
Power-up Sequence
The AU1500 processor power structure is designed such that the external I/O voltage (VDDX) is driven separately from the core voltage (VDDI). In this way the core voltage can be sourced at lower voltages saving power. In addition the AU1500 processor is designed to allow the system designer to remove the core voltage during Sleep to maximize power efficiency. Two signals VDDXOK and PWR_EN are used to facilitate this power strategy. VDDXOK is used as a signal to the processor that power on VDDX is stable. Stable is defined as having reached 90% of its nominal value. PWR_EN is an output from the AU1500 that is asserted after VDDXOK is asserted and can be used as an enable to the regulator that is providing the core voltage, VDDI. The following describes the power-up sequence for the AU1500 processor: 1) 2) 3) Apply VDDX (3.3V I/O power). When VDDX has reached 90% of nominal, assert VDDXOK. The AU1500 processor then asserts PWR_EN which can be used to enable the regulator driving VDDI (CPU power).
Figure 9-1 shows the power-up sequence, including arrows representing causal dependencies. For the timing specifications of this sequence, refer to Section 12.7.1 "Power-up Sequence Timing" on page 230.
VDDX VDDXOK
PWR_EN
VDDI
Figure 9-1. Power-up Sequence
AMD AlchemyTM AU1500TM Processor Data Book
180
www..com
Power-up, Reset and Boot 30361D
9.2
Reset
A hardware reset is defined as a reset in which both VDDXOK and RESETIN# are toggled. Typically this happens only at power-on, but a system designer can choose to tie VDDXOK and RESETIN# together in which case all resets will be hardware resets. For a runtime reset, power remains applied and only the RESETIN# signal is toggled. Note that certain registers, specifically some of those in the system control block, are not affected by this type of reset. See the register description for the register in question for more information. If a register is not reset to defaults by both hardware reset and runtime reset, it is noted in the register description.
9.2.1
Hardware Reset
For a hardware reset, VDDXOK makes a transition from low to high followed by RESETIN# negating (transitioning from low to high). The following sequence describes a hardware reset: 1) 2) 3) ROMSEL and ROMSIZE should be terminated in the design so the appropriate boot type occurs. These values should not change during runtime. At the same time or after VDDXOK is asserted, RESETIN# can be negated. In other words, RESETIN# can not be negated before VDDXOK is asserted. This allows VDDXOK and RESETIN# to be tied together. RESETOUT# is negated after RESETIN# is negated.
Figure 9-2 shows the hardware reset sequence, including arrows representing causal dependencies. For the timing specifications of this sequence, refer to Section 12.7.2 "Hardware Reset Timing" on page 231.
VDDXOK RESETIN# RESETOUT#
Figure 9-2. Hardware Reset Sequence 9.2.2
1) 1) 2) 3)
Runtime Reset
During runtime (after power is stable) the reset sequence can be broken down as follows: During a runtime reset it is assumed that VDDX and VDDI remain at their nominal voltage. In addition, VDDXOK must remain asserted; otherwise, a hardware reset will occur. PWR_EN remains asserted by the AU1500 processor. RESETIN# is held asserted long enough to be recognized as a valid reset. The processor acknowledges the reset by asserting RESETOUT#. After RESETIN# is released, the processor signals the end of the reset by negating RESETOUT#.
Note that certain registers (specifically those in the system control block) are not affected by a runtime reset. Note also that ROMSEL and ROMSIZE should already be terminated in the design so the appropriate boot type occurs--these values should not change during runtime. Figure 9-3 shows the runtime reset sequence, including arrows representing causal dependencies. For the timing specifications of this sequence, refer to Section 12.7.3 "Runtime Reset Timing" on page 232.
AMD AlchemyTM AU1500TM Processor Data Book
181
www..com
30361D Power-up, Reset and Boot
VDDX (at nominal voltage) VDDXOK (asserted high) PWR_EN (remains asserted) VDDI (at nominal voltage) RESETIN# RESETOUT#
Figure 9-3. Runtime Reset Sequence
9.3
Boot
For both hardware and runtime resets, the CPU boots from KSEG1 address 0xBFC0 0000 which is translated to physical address 0x0 1FC0 0000; therefore, the system designer should place the start of the boot code at 0x0 1FC0 0000. The ROMSEL and ROMSIZE signals determine the boot device type and width according to Table 9-1. The system designer should configure ROMSEL and ROMSIZE appropriately. Note that ROMSEL and ROMSIZE should not change during runtime.
Table 9-1. ROMSEL and ROMSIZE Boot Device
ROMSEL 0 0 1 1 ROMSIZE 0 1 0 1 Boot Device Type and Width Boot from 32-bit ROM interface. Boot from 16-bit ROM interface. Boot from 32-bit SMROM interface and Sync Flash boot. Boot from PCI memory space.
RCS0# is configured to be enabled for 0x0 1FC0 0000 at default when booting from a ROM device (ROMSEL = 0, ROMSIZE = x). See Section 3.2 "Static Bus Controller" on page 53, for more information about the default timing and size of the address enabled at reset. SDCS0# is configured to be enabled for 0x0 1FC0 0000 at default when booting from a SMROM device (ROMSEL = 1, ROMSIZE = 0). See Section 3.1 "SDRAM Memory Controller" on page 44, for more information about the default timing and size of the address enabled at reset.
9.3.1
Endianness and 16-Bit Static Bus Boot
When booting from a 16-bit chip select on the static bus, the system designer must be sure the data format (endianness) is consistent across the Au1 core, the static bus controller, and the software image itself. This section describes how to make endianness consistent for both little- and big-endian systems. For more on how the endian mode affects the behavior of 16-bit static bus chip selects, see "Halfword Ordering and 16-bit Chip Selects" on page 70. Note: When programming ROM or Flash devices with a part programmer, take care to ensure that the programmer is not swapping bytes or halfwords erroneously. The configuration of the part programmer is often a source of error when initially bringing-up a new design.
182
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Power-up, Reset and Boot 30361D
9.3.2
16-Bit Boot for Little-Endian System
Booting from 16-bit ROM or Flash in a system that is intended to run the Au1 core in little-endian mode is very straightforward. Generally speaking, the boot code and/or the application is compiled for little-endian. Because the the Au1 core defaults to big-endian mode, the boot code must change the Au1 core endianness to little-endian before any data accesses (to the 16-bit chip-select). The resulting boot code and/or application image is placed in the ROM/Flash memory in the littleendian format. Even though the Au1 core starts in big-endian mode, the static bus controller properly retrieves instructions needed to boot the system since the application image is in little-endian format and the static bus controller defaults to little-endian ordering out of reset.
9.3.3
16-Bit Boot for Big-Endian System
Booting from 16-bit ROM or Flash in a system that is intended to run the Au1 core in big-endian mode is very straightforard, but does need one extra, important step. Generally speaking, the boot code and/or the application is compiled for big-endian. The boot code must set the mem_stcfg[BE] bit before it can properly fetch/reference the big-endian image. The resulting boot code and/or application image is placed in the ROM/Flash memory in the big-endian format. In this situation, there is the dilema that, out of reset, the Static Bus controller defaults to little-endian ordering, but the application image itself is in big-endian format. The solution is to place the following code at the reset exception vector (KSEG1 address 0xBFC 00000, physical adddress 0x0 1FC0 0000): .long .long .long .long .long .long .long .long .long 0xb4003c08 0x10003508 0x00008d09 0x02003529 0x0000ad09 0x00000000 0x00000000 0x00000000 0x00000000 # # # # # # # # # lui ori lw ori sw nop nop nop nop t0,0xb400 t0,t0,0x1000 t1,0(t0) t1,t1,0x200 t1,0(t0)
The code does a read-modify-write of register mem_stcfg0 to set the BE bit. The values in the .long statements above are the halfword-swapped opcodes of the instructions in the comments to the right. With this technique, these first few instructions are actually in the little-endian format to match the static bus controller out of reset, and set mem_stcfg[BE] which in turns allows the remainder of the big-endian memory contents to be accessed properly. The NOPs are necessary to ensure that the Au1 core pipeline does not contain incorrectly [halfword swapped] prefetched instructions. Note too that the NOP opcode 0x00000000 is the same instruction regardless of endian ordering. Note: The boot code should set mem_stcfg0[BE] as early as possible, preferrably as the first activity. It is especially important to ensure that no cachable accesses take place to the 16-bit device, else the cache will contain the halfword swapped contents of the 16-bit memory.
9.3.4
System Boot
For system debug, the processor can be configured to boot from the EJTAG probe through the EJTAG port; see Section 10.0 "EJTAG Implementation" on page 184 for more information.
AMD AlchemyTM AU1500TM Processor Data Book
183
www..com
EJTAG Implementation 30361D
10.0EJTAG Implementation
The AU1500 processor implements EJTAG following the MIPS' EJTAG 2.5 Specification. This section presents the EJTAG implementation on the AU1500 processor while concentrating on those features from the EJTAG 2.5 specification which are implementation specific. In addition, those features which have not been implemented or any differences in the AU1500 processor implementation of EJTAG from the rev 2.5 specification are also noted. It is assumed that the EJTAG 2.5 specification will be referenced for implementation details not covered here. If a particular bit is not implemented it can be assumed that the functionality associated with the bit is not implemented or not applicable unless otherwise noted. The following features comprise the EJTAG implementation on the AU1500 processor: * Extended instructions SDBBP and DERET * Debug exceptions * Extended CP0 registers DEBUG, DEPC and DESAVE * EJTAG memory range 0xFF200000-0xFF3FFFFF * Instruction/data breakpoints through the watch exception (specific to AU1500) * Processor bus breakpoints (from EJTAG 2.0) * Memory overlay (from EJTAG 2.0) * EJTAG tap per IEEE1149.1 Note that the optional data and instruction breakpoint features from the EJTAG 2.5 specification are not implemented.
10
10.1
EJTAG Instructions
Both SDBBP and DERET are supported by the AU1500 processor: * SDBBP causes a Debug Breakpoint exception. * DERET is used to return from a Debug Exception.
10.2
Debug Exceptions
The following exceptions will cause entry into debug mode. * DSS - debug single step * DINT - debug interrupt, processor bus break * DBp - execution of SDBBP instruction * DWATCH - debug watch exception. AU1500 processor-specific implementation allowing CPU watch exception to cause debug exception. See description of the Section 10.4.2.6 "EJWatch Register (TAP Instruction EJWATCH)" on page 198 register. Note that other normal exceptions, when taken in debug mode, will be handled by the debug exception handler.
AMD AlchemyTM AU1500TM Processor Data Book
184
www..com
EJTAG Implementation 30361D
10.3
Coprocessor 0 Registers
The Coprocessor 0 Registers for EJTAG are shown in Table 10-1.
Table 10-1. Coprocessor 0 Registers for EJTAG
Register Number 23 24 31 Select 0 0 0 Name debug depc desave Description Debug indications and controls for the processor Program Counter at last debug exception or exception in debug mode Debug exception save register
10.3.1
Debug Register (CP0 Register 23, Select 0)
The Debug register contains the cause of the most recent debug exception and exception in Debug Mode. It also controls single stepping. Only the DM bit and the EJTAGver field are valid when read from the Debug register in Non-Debug Mode; the value of all other bits and fields is UNPREDICTABLE. The following bits and fields are updated only on debug exceptions and/or exceptions in Debug Mode: * DSS, DBp, DINT are updated on both debug exceptions and on exceptions in Debug Modes. * DExcCode is updated on normal exceptions in Debug Mode, and is undefined after a debug exception. * DBD is updated on both debug and on normal exceptions in Debug Modes.
debug Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 DD DM ND LS CD VER DEXCOSE NS SS Def. x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x 0 0 0 CP0 Register 23, Select 0 6543210 DI DB DS 0x000xx
Bits 31
Name DD
Description DBD. Indicates whether the last debug exception or exception in Debug Mode occurred in a branch or jump delay slot. 0 1 Not in delay slot In delay slot
R/W R
Default UNPRED
30
DM
Indicates that the processor is operating in Debug Mode. 0 1 Processor is operating in Non-Debug Mode Processor is operating in Debug Mode
R
0
29 28
ND LS
NoDCR. 0 DSEG is present. LSNM. Controls access of loads/stores between dseg and remaining memory when dseg is present and while in debug mode. 0 1 Loads/stores in dseg address range go to dseg Loads/stores in dseg address range go to system memory
R R/W
0 0
27 26 25 24 23 22
-- -- CD -- -- --
Reserved, should be cleared. This bit is called Doze in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called Halt in the EJTAG 2.5 specification and was not implemented. CountDM. This bit is 0, indicating that the counter will be stopped in debug mode. Reserved, should be cleared. This bit is called IBusEP in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called MCheckP in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called CacheEP in the EJTAG 2.5 specification and was not implemented.
R R R R R R
0 0 0 0 0 0
AMD AlchemyTM AU1500TM Processor Data Book
185
www..com
30361D EJTAG Implementation
Bits 21 20 19 18 17:15 14:10
Name -- -- -- -- VER DEXCODE
Description Reserved, should be cleared. This bit is called DBusEP in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called IEXI in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called DDBSImpr in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called DDBLImpr in the EJTAG 2.5 specification and was not implemented. EJTAGver. 1 EJTAG Version 2.5 DExcCode. Indicates the cause of the latest exception in Debug Mode. The field is encoded as the ExcCode field in the Cause register for those exceptions that can occur in Debug Mode (the encoding is shown in the MIPS32 specification), with addition of code 30 with the mnemonic CacheErr for cache errors. This value is undefined after a debug exception.
R/W R R R R R R
Default 0 0 0 0 1 UNPRED
9 8
NS SS
NoSSt. 0 0 1 Single step is implemented. SSt. Controls whether single-step feature is enabled: No enable of single-step feature Single-step feature enabled
R R/W
0 0
7:6 5
-- DI
Reserved, should be cleared. DINT. Indicates that a Debug Interrupt exception occurred. This could be either a Processor Bus Break (indicated by BS0 in the Processor Bus Break Status Register) or EJTAG break. The BS0 bit should be checked to see what caused the exception. Cleared on exception in Debug Mode. 0 1 No Debug Interrupt exception Debug Interrupt exception
R R
0 UNPRED
4 3 2 1
-- -- -- DB
Reserved, should be cleared. This bit is called DIB in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called DDBS in the EJTAG 2.5 specification and was not implemented. Reserved, should be cleared. This bit is called DDBL in the EJTAG 2.5 specification and was not implemented. DBp. Indicates that a Debug Breakpoint exception occurred. Cleared on exception in Debug Mode. 0 1 No Debug Breakpoint exception Debug Breakpoint exception
R R R R
0 0 0 UNPRED
0
DS
DSS. Indicates that a Debug Single Step exception occurred. Cleared on exception in Debug Mode. 0 1 No debug single-step exception Debug single-step exception
R
UNPRED
186
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
10.3.2
Debug Exception Program Counter Register
The Debug Exception Program Counter (DEPC) register is a read/write register that contains the address at which processing resumes after the exception has been serviced. Hardware updates this register on debug exceptions and exceptions in Debug Mode. For precise debug exceptions and precise exceptions in Debug Mode, the DEPC register contains either: * The virtual address of the instruction that was the direct cause of the exception; or * the virtual address of the immediately preceding branch or jump instruction, when the exception-causing instruction is in a branch delay slot, and the Debug Branch Delay (BDB) bit in the Debug register is set. For imprecise debug exceptions and imprecise exceptions in Debug Mode, the DEPC register contains the address at which execution is resumed when returning to Non-Debug Mode.
depc - Debug Exception Program Counter Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DEPC[31:0] Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 Register 24, Select 0 6543210 0 0 0 0 0 0 0
9 0
8 0
7 0
Bits 31:0
Name DEPC
Description Debug Exception Program Counter
R/W R/W
Default UNPRED
10.3.3
Debug Exception Save Register
The Debug Exception Save (DESAVE) register is a read/write register that functions as a simple scratchpad register. The debug exception handler uses this to save one of the GPRs, which is then used to save the rest of the context to a predetermined memory area, for example, in the dmseg. This register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed.
desave - Debug Exception Save Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DESAVE[31:0] Def. x x x x x x x x x x x x x x x x x x x x x x CP0 Register 31, Select 0 6543210 x x x x x x x
9 x
8 x
7 x
Bits 31:0
Name DESAVE
Description Debug Exception Save contents
R/W R/W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
187
www..com
30361D EJTAG Implementation
10.4
EJTAG Memory Range
In debug mode accesses to virtual 0xFF200000-0xFF3FFFFF bypass translation. The debug memory is split into two logical divisions: * dmseg: 0xFF20 0000-0xFF2F FFFF * drseg: 0xFF30 0000-0xFF3F FFFF Note that the physical address addr[35:32] of this range is zero. dmseg is the memory range that will be serviced by the probe TAP in debug mode for all instruction accesses to this virtual address range and for data accesses if the LSNM in the Debug Register is 0. drseg is the memory range containing the EJTAG memory mapped registers and is accessible when LSNM in the Debug Register is 0.
10.4.1
EJTAG Memory Mapped Registers
Table 10-2 shows the EJTAG memory mapped registers located in drseg.
Table 10-2. EJTAG Memory Mapped Registers at 0xFF300000
Offset 0x0000 0x000C 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 Register dcr pbs pab pdb pdm pbcam phab pham Description Debug Control Register Processor Break Status Processor Address Bus Break Processor Data Break Processor Data Mask Processor Control/Address Mask Processor High Address Break Processor High Address Mask
The EJTAG implementation in the AU1500 processor does not employ data breakpoints and instruction breakpoints as described in the EJTAG 2.5 specification. Instead it offers Processor breakpoints as described in the EJTAG 2.0.0 specification. The Processor Bus Match registers monitor the bus interface of the MIPS CPU and provide debug exception or trace trigger for a given physical address and data. In addition, the implementation allows the CPU watchpoints to cause a debug exception. This functionality is enabled through the EJTAG TAP port. Please see Section 10.4.2.6 "EJWatch Register (TAP Instruction EJWATCH)" on page 198 for details.
188
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
10.4.1.1 Debug Control Register The Debug Control Register (DCR) controls and provides information about debug issues. The width of the register is 32 bits. The DCR is located in the drseg at offset 0x0000.
dcr - Debug Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EN DB IB Def. 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0000 43210 IE NE NP SR PE 11010
9 0
8 0
7 0
6 0
5 0
Bits 31:30 29 28:18 17 16 15:5 4
Name -- EN -- DB IB -- IE
Description Reserved, should be cleared. ENM. 1 Processor is big Endian in both debug and kernel mode. Reserved, should be cleared. DataBrk. 0 0 IntE. 1 Interrupt enabled in debug mode depending on other enabling mechanisms. No data hardware breakpoints implemented. InstBrk. No instruction hardware breakpoints implemented. Reserved, should be cleared.
R/W R R R R R R R
Default 0 1 0 0 0 0 1
3
NE
NMIE. 1 Non-Maskable Interrupt is enable for non-debug mode.
R
1
The NMI is not implemented in the AU1500 so this bit has no applicability. 2 NP NMIPend. 0 No NMI pending. The NMI is not implemented in the AU1500 so this bit has no applicability. 1 SR SRstE. 1 Soft reset is fully enabled. Soft Reset is not implemented in the AU1500 so this bit has no applicability. 0 PE ProbEn. Indicates value of the ProbEn value in the ECR register. 0 1 No access should occur to dmseg Probe services accesses to dmseg R Same value as ProbEN in ECR R 1 R 0
AMD AlchemyTM AU1500TM Processor Data Book
189
www..com
30361D EJTAG Implementation
10.4.1.2
Processor Bus Break Status Register
9 0 8 0 7 0 6 0 5 0 4 0 Offset = 0x000C 3210
BS
pbs - Processor Bus Break Status Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OLP BCN
Def. 0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits 31 30 29:28 27:24 23:15 14:1
Name -- OLP -- BCN -- --
Description Reserved, should be cleared. 1 Memory overlay functionality is implemented for processor breaks. Reserved, should be cleared. Number of Processor Breaks. 1 One Channel has been implemented for the Processor Bus Break. Reserved, should be cleared. Reserved, should be cleared. These bits are the Bsn bits in the EJTAG 2.0.0 specification and are not needed since only one break is implemented. Break Status. This bit, when set, indicates that a processor bus break or processor bus trigger has occurred. BS can be cleared by activating PrRst (EJTAG CONTROL Register), hard reset and also by writing a `0' to it. The Debug handler must clear this bit before returning from debug mode.
R/W R R R R R R
Default 0 1 0 1 0 0
0
BS
R/W
0
10.4.1.3 Processor Address Bus Break This register contains the bits of the physical Processor Address Bus Break.
pab - Processor Address Bus Break Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PAB[31:0] Def. x x x x x x x x x x x x x x x x x x x x x x Offset = 0x0300 3210 x x x x
9 x
8 x
7 x
6 x
5 x
4 x
Bits 31:0
Name PAB
Description Processor Address Bus Break 0. This index contains the lower 32 bits of the physical address. In combination with the high order address bits, these bits make up the break address.
R/W R
Default UNPRED
10.4.1.4 Processor Data Bus Break This register specifies the data value for the Processor Data Bus match.
pdb - Processor Data Bus Break Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PDB[31:0] Def. x x x x x x x x x x x x x x x x x x x x x x Offset = 0x0304 3210 x x x x
9 x
8 x
7 x
6 x
5 x
4 x
Bits 31:0
Name PDB
Description Processor Data Bus Break 0. This index contains the 32 bits of the data bus match.
R/W R
Default UNPRED
190
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
10.4.1.5 Processor Data Mask/Upper Overlay Address Mask This register is dual purpose depending on the value of the Overlay Enable bit in the Bus Break Control and Address Mask. This register specifies the mask value for the Processor Data Mask register. Each bit corresponds to a bit in the data register.
pdm_uoam - Processor Data Mask Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PDM[31:0] Def. x x x x x x x x x x x x x x x x x x x x x x Offset = 0x0308 3210 x x x x
9 x
8 x
7 x
6 x
5 x
4 x
Bits 31:0
Name PDM
Description Applies only when OE not enabled. Processor Data Mask 0. When OE in the pbcam register is not enabled. 0 1 Data bit is not masked, data bit is compared. Data bit is masked, data bit is not compared.
R/W R
Default UNPRED
31:24
UOAM
Applies only when OE is enabled. Upper Overlay Address Mask. These bits represent bits 31:24 of the address mask and are combined with the LAM and HAM fields to create a complete 36 bit address mask. 0 1 Address bit is not masked, address bit is compared. Address bit is masked, address bit is not compared.
R/W
UNPRED
Note that bits [23:0] are not used when OE is set and should be written 0.
10.4.1.6 Processor Bus Break Control and Address Mask This register selects the Processor Bus match function to enable debug break or trace trigger. It also includes control bits to enable comparison as well as mask bits to exclude address bits from comparison. Note that all processor break exceptions are imprecise.
pbcam - Bus Break Control and Address Mask Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LAM[31:8] Def. x x x x x x x x x x x x x x x x x x x x x x Offset = 0x030C 76543210 DC DU DIU OE BE xxxxx0000
9 x
8
Bits 31:8
Name LAM
Description Address Mask. These bits specify the mask value for the 24 lower bits of the Processor Address register (PBA0[23..0]). Each bit corresponds to the same bit in PBA0. 0 1 Address bit is not masked, address bit is compared. Address bit is masked, address bit is not compared.
R/W R/W
Default UNPRED
7
DC
Data Store to Cached Area. This bit enables the comparison on Processor Address and Data Bus for Data Store to the Cached area. 0 1 Processor Address and Data is not compared for storing data to the Cached area. Processor Address and Data is compared for storing data to the Cached area.
R/W
UNPRED
6
DU
Data Store To Uncached Area. This bit enables the comparison on Processor Address and Data Bus for Data Store to the uncached area. 0 1 Processor Address and Data is not compared for storing data into the un-cached area. Processor Address and Data is compared for storing data into the uncached area.
R/W
UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
191
www..com
30361D EJTAG Implementation
Bits 5:4
Name DIU
Description Data or Instruction fetch or load from Uncached Area. These bits enable the comparison on Processor Address and Data Bus for Data or Instruction load and fetch from the un-cached area. 00 11 Processor Address and Data is not compared for loading data or fetching instruction from the un-cached area. Processor Address and Data is compared for loading data or fetching instruction from the un-cached area.
R/W R
Default UNPRED
Bits 5 and 4 were named ILUC and DFUC in the EJTAG 2.0.0 specification and were implemented separately for instruction and data fetches. 3 OE Overlay Enable. When this bit is 1 and the processor physical address, masked by the HAM, UOAM and the LAM fields (all 36 bits of the address mask), matches the PHAB and PAB registers, then the memory request is redirected to the EJTAG Probe. The processor bus break can not be used for normal break, function if the OLE bit is set, so BE must be set to 0. The behavior is otherwise undefined. Overlay is only valid for memory regions. It is not valid for I/O or debug space and the behavior is unpredictable if addresses within this space are used. 2 1 0 -- -- BE Reserved, should be cleared. This bit is called TE in the EJTAG 2.0.0 specification and was not implemented. Reserved, should be cleared. This bit is called CBE in the EJTAG 2.0.0 specification and was not implemented. Break Enable. This bit enables the Processor Bus break function. 0 1 Processor Bus break function is disabled. Processor Bus break function is enabled. R R R/W 0 0 0 R/W 0
If Break Enable is set and the processor physical address, masked by the HAM and the LAM fields (UOAM is only for overlay so bits 31:24 are not masked here), matches the PHAB and PAB registers, and the processor data bus matches the PDB register (masked by PDM), then a debug exception to the processor is generated. The BS bit in the Processor Bus Break Status register is set and the DINT bit in the Debug Register is set. If the debug exception handler is already running (DM=`1'), then the debug exception will not be taken until DM = 0. This functionality is mutually exclusive to OLE so only one of OLE or BE should be set at any time.
192
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
10.4.1.7 Processor High Address Bus Break This register specifies the high order address for the processor address bus break.
pha - Processor High Address Bus Break Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0310 3210 HA[3:0] 0XXXX 4
9 0
8 0
7 0
6 0
5 0
Bits 31:4 3:0
Name -- HA
Description Reserved, should be cleared. These bits map to the high physical address bits 35:31.
R/W R R/W
Default 0 UNPRED
10.4.1.8 Processor High Address Mask This register specifies the high order address mask for the processor address bus break.
pham - Processor High Address Mask Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Def. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset = 0x0314 3210 HAM[3:0] 0XXXX 4
9 0
8 0
7 0
6 0
5 0
Bits 31:4 3:0
Name -- HAM
Description Reserved, should be cleared. High Address Mask for address bits [35:31]. 0 1 Data bit is not masked, data bit is compared Data bit is masked, data bit is not compared
R/W R R/W
Default 0 UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
193
www..com
30361D EJTAG Implementation
10.4.2
EJTAG Test Access Port (TAP)
The EJTAG TAP contains the 5 TAP pins and a 16 state controller with a 5 bit instruction register. Table 10-3 shows the 5-bit instructions supported by the AU1500.
Table 10-3. EJTAG Instruction Register Values
Hex Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E-0x1B 0x1C 0x1D-0x1E 0x1F Instruction EXTEST IDCODE SAMPLE IMPCODE -- -- -- -- ADDRESS DATA CONTROL ALL EJTAGBOOT NORMALBOOT -- EJWATCH -- BYPASS Function Boundary Scan Selects ID Register Boundary Scan Sample/Preload (IEEE JTAG Instruction) Selects Implementation Register Reserved This reserved register is for test mode HIZ - TRI-STATE all output pins and Select Bypass register. This reserved register is for test mode CLAMP - IEEE Clamp pins and select bypass register. Reserved Selects Address Register. Selects Data Register. Selects EJTAG Control Register. Selects the Address, Data and EJTAG Control registers. Makes the processor take a debug exception after reset. Makes the processor execute the reset handler after reset. Reserved Selects Watch register Reserved Bypass mode
10.4.2.1 Device Identification (ID) Register The Device ID register is a 32-bit read-only register that identifies the specific device implementing EJTAG.
IDCODE - Device Identification Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VER PNUM Def. 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 TAP Instruction IDCODE 76543210 MANID 10001111
9 1
8 0
Bits 31:28 27:12 11:1
Name VER PNUM MANID
Description Identifies the version of the device. Identifies the part number of the device. Identifies the manufacturer ID code for the device. MANID[6:0] are derived from the last byte of the JEDEC code with the parity bit discarded. MANID[10:7] provides a binary count of the number of bytes in the JEDEC code that contain the continuation character (0x7F). When the number of continuations characters exceeds 15, these four bits contain the modulo16 count. This bit is reserved and should be written a 1.
R/W R R R
Default 0 0x03E8 0x147
0
--
R
1
194
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
10.4.2.2 Implementation Register The Implementation register is a 32-bit read-only register that identifies features implemented in this EJTAG compliant processor, mainly those accessible from the TAP.
IMPCODE - Implementation Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VER R3 DI AS M16 ND
9 0
8 0
7 0
TAP Instruction IMPCODE 6543210
M32
Def. 0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Bits 31:29 28 27:25 24 23 22:21 20:17 16 15 14 13:1 0
Name EJTAGver R3 -- DI -- AS -- M16 -- ND -- MIPS32/64
Description 1 0 0 10 0 1 0 EJTAG version 2.5 R3k privileged environment DINT signal from the probe is not supported. 8-bit ASID No MIPS16 support No EJTAG DMA support 32-bit processor
R/W R R R R R R R R R R R R
Default 1 0 0 0 0 10 0 0 0 1 0 0
Reserved, should be cleared. Reserved, should be cleared. Reserved, should be cleared. Reserved, should be cleared. Reserved, should be cleared.
10.4.2.3 Data Register The read/write Data register is used for opcode and data transfers during processor accesses. The width of the Data register is 32 bits. The value read in the Data register is valid only if a processor access for a write is pending, in which case the data register holds the store value. The value written to the Data register is only used if a processor access for a pending read is finished afterwards, in which case the data value written is the value for the fetch or load. This behavior implies that the Data register is not a memory location where a previously written value can be read afterwards.
DATA Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DATA[31:0] Def. X X X X X X X X X X X X X X X X X X X X X X X TAP Instruction DATA or ALL 76543210 X X X X X X X X
8 X
Bits 31:0
Name DATA
Description Data used by processor access
R/W R/W
Default UNPRED
AMD AlchemyTM AU1500TM Processor Data Book
195
www..com
30361D EJTAG Implementation
10.4.2.4 Address Register The read-only Address register provides the address for a processor access. The width of the register is 36 bits. The value read in the register is valid if a processor access is pending, otherwise the value is undefined. The two LSBs of the register are used with the Psz field from the EJTAG Control register to indicate the size and data position of the pending processor access transfer. These bits are not taken directly from the address referenced by the load/store (i.e. these bits are encoded with Psz).
ADDRESS TAP Instruction ADDRESS or ALL Bit 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRESS[36:0] Def X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bits 35:0
Name Address
Description Address used by processor access
R/W R
Default UNPRED
10.4.2.5 EJTAG Control Register (ECR) The 32-bit EJTAG Control Register (ECR) handles processor reset, Debug Mode indication, access start, finish, and size and read/write indication. The ECR also: * Controls debug vector location and indication of serviced processor accesses. * Allows debug interrupt request. * Indicates processor low-power mode. The EJTAG Control register is not updated/written in the Update-DR state unless the Reset occurred; that is RO (bit 31) is either already 0 or is written to 0 at the same time. This condition ensures proper handling of processor accesses after a reset. Bits that are R/W in the register return their written value on a subsequent read, unless other behavior is defined. Internal synchronization hardware thus ensures that a written value is updated for reading immediately afterwards, even when the TAP controller takes the shortest path from the Update-DR to Capture-DR state. Note: To ensure a write is successful to the PE, PT and EB bits when the processor is undergoing a clock change (for PLL lock/relock), the host must continue writing these bits until the write is verified by reading the change. Failure to do this could result in the write of these bits being lost. Reset of the processor can be indicated in the TCK domain a number of TCK cycles after it is removed in the processor clock domain in order to allow for proper synchronization between the two clock domains.
ECR - EJTAG Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RO PSZ DZ PRW PA PR PE PT EB
9 0
TAP Instruction CONTROL or ALL 876543210
DM
Def. 1
x
x
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits 31
Name RO
Description Indicates if a processor reset has occurred since the bit was cleared: 0 1 No reset occurred Reset occurred
R/W R/W0
Default 1
The RO bit stays set as long as reset is applied. This bit must be cleared to acknowledge that the reset was detected. The EJTAG Control register is not updated in the Update-DR state unless RO is 0 or written to 0 at the same time. This is in order to ensure correct handling of the processor access after reset.
196
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
Bits 30:29
Name PSZ
Description Indicates the size of a pending processor access, in combination with the Address register. 00 01 10 11 Byte Halfword Word Triple
R/W R
Default UNPRED
This field is valid only when a processor access is pending; otherwise, the read value is undefined. 28:23 22 -- DZ Reserved, should be cleared. Doze. Indicates if the processor is in a WAIT state: 0 1 21 20 19 -- -- PRW Processor is not in a wait state. Processor is in a wait state. R R R 0 0 UNPRED R R 0 0
Reserved, should be cleared. This bit is called Halt in the EJTAG 2.0.0 specification and was not implemented. Reserved, should be cleared. This bit is called PerRst in the EJTAG 2.0.0 specification and was not implemented. Indicates read or write of a pending processor access. 0 1 Read processor access, for a fetch/load access Write processor access, for a store access
This value is defined only when a processor access is pending. 18 PA Indicates a pending processor access and controls finishing of a pending processor access. When read: 0 1 No pending processor access Pending processor access R/W0 0
A write of 0 finishes a processor access if pending; otherwise operation of the processor is UNDEFINED if the bit is written to 0 when no processor access is pending. A write of 1 is ignored. 17 16 -- PR Reserved, should be cleared. Controls the processor reset. 0 1 No processor reset applied Processor reset applied R R/W 0 0
Setting this bit to 1 will apply a processor reset. When this bit is read back it will always read a 0. Note that startup latencies should be observed when applying reset. 15 PE Controls indication to the processor of whether the probe expects to handle accesses to EJTAG memory through servicing of processor accesses. 0 1 Probe does not service processor accesses Probe will service processor accesses R/W Determined by EJTAGBOOT
The ProbEn bit is reflected as a read-only bit in the Debug Control Register (DCR) bit 0. When a read from this bit shows a change, the new value has taken effect in the DCR. This handshake mechanism ensures that the setting from the TCK clock domain takes effect in the processor clock domain. However, a change of the ProbEn prior to setting the EjtagBrk bit is ensured to affect execution of the debug handler due to the debug exception. Not all combinations of ProbEn and ProbTrap are allowed. Please see the previous note about writing this bit (in Section 10.4.2.5 "EJTAG Control Register (ECR)" on page 196).
AMD AlchemyTM AU1500TM Processor Data Book
197
www..com
30361D EJTAG Implementation
Bits 14
Name PT
Description Controls location of the debug exception vector: 0 1 Normal memory 0xBFC0 0480 EJTAG memory 0xFF20 0200
R/W R/W
Default Determined by EJTAGBOOT
When a read from this bit shows a change, the new value has taken effect in the DCR. This handshake mechanism ensures that the setting from the TCK clock domain takes effect in the processor clock domain. However, a change of the ProbTrap prior to setting the EjtagBrk bit is ensured to affect execution of the debug handler due to the debug exception. Not all combinations of ProbEn and ProbTrap are allowed. Please see the previous note about writing this bit (in Section 10.4.2.5 "EJTAG Control Register (ECR)" on page 196). 13 12 -- EB Reserved, should be cleared. Requests a debug interrupt exception to the processor when this bit is written as 1. This bit is cleared by hardware when the processor enters debug mode. If software then sets EB while the processor is already in debug, the request is not ignored but is delayed. That is, once the processor returns to normal mode, the pending debug exception request immediately sends the processor back into debug. A write of 0 is ignored. The debug request restarts the processor clock if the processor was in a wait mode, which stopped the processor clock. The read value indicates a pending Debug Interrupt exception requested through this bit: 0 1 No pending Debug Interrupt exception requested through this bit Pending Debug Interrupt exception R R/W1 0 Determined by EJTAGBOOT
The read value can, but is not required to, indicate other pending DINT debug requests (for example, through the DINT signal). Please see the previous note about writing this bit (in Section 10.4.2.5 "EJTAG Control Register (ECR)" on page 196). 11:4 3 -- DM Reserved, should be cleared Indicates if the processor is in Debug Mode. 0 1 2:0 -- Processor is in Non-Debug Mode Processor is in Debug Mode R 0 R R 0 0
Reserved, should be cleared.
10.4.2.6 EJWatch Register (TAP Instruction EJWATCH) The EJWatch register is used to enable CPU watchpoints to cause a debug exception. This functionality is unique to the AU1500.
EJWATCH Bit Def. 7 0 6 0 5 0 4 0 TAP Instruction EJWATCH 3 2 1 0 WATCH 0 0 0 0
Bits 7:3 2 1
Name -- -- --
Description Reserved, should be cleared. Reserved, should be cleared. This bit is the Global Scan test bit. Reserved, should be cleared. This bit is a Test Mode bit.
R/W R R R
Default 0 0 0
198
AMD AlchemyTM AU1500TM Processor Data Book
www..com
EJTAG Implementation 30361D
Bits 0
Name WATCH
Description This bit controls the debug functionality of the CPU watch register. 0 1 Normal Watch Exception Mode Debug Watch Exception Mode
R/W R/W
Default 0
- Blocks writes to Watch register in non-debug mode - Watch Exception will become debug exceptions with DEXCODE=23 - The PC will be saved in the DEPC (not in the EPC as with a normal watch exception). Note that the Status, Cause, and EPC will not be affected by a debug watch exception when this bit is enabled.
10.4.2.7 Bypass Register (TAP Instruction BYPASS) The Bypass register is a one-bit read-only register, which provides a minimum shift path through the TAP. This register is also defined in IEEE 1149.1.
BYPASS Bit Def. TAP Instruction BYPASS 0 BP 0
Bits 0
Name BP
Description Ignored on writes; returns zeros on reads.
R/W R
Default 0
10.4.3
EJTAG TAP Hardware Considerations
The EJTAG interface consists of the signals listed in Table 10-4.
Table 10-4. EJTAG Signals
Signal TRST# TDI TDO TMS TCK Input/Output I I O I I Definition Asynchronous TAP reset Test data input to the instruction or selected data registers. This signal will be sampled on the rising edge of TCK Test data output from the instruction or data register. This signal will transition on the falling edge (valid on rising edge) of TCK Control signal for TAP controller. This signal is sampled on the wising edge of TCK. Control clock for updating TAP controller and shifting data through instruction or selected data register.
Note that the EJTAG TAP signal TCK must always be less than 1/4 the System Bus (SBUS) clock speed for proper operation. In addition, termination as shown in EJTAG 2.5 spec must be followed.
AMD AlchemyTM AU1500TM Processor Data Book
199
www..com
Signal Descriptions 30361D
11.0Signal Descriptions
This section describes the external signals on the AU1500 processor.
11
In order to maximize the functionality of the AU1500 processor, many of the pins have multiple uses. Note that if a pin is configured for one use, any other functionality associated with that pin can not be utilized at the same time. In other words a pin can not be used as a general-purpose I/O signal at the same time it is assigned to a peripheral device. (See Section 8.3.1 "Pin Functionality" on page 168.) Figure 11-1 on page 201 shows the external signals of the AU1500 processor. All signals are grouped according to their functional block. Signals that share a pin are listed with the multiplexed signal name in parentheses--the signal name shown in bold is the default. Note: A signal with an "#" is active-low; that is, the signal is considered asserted (active) when low and negated when high. Active-high signals (no #) are considered asserted when high and negated when low.
AMD AlchemyTM AU1500TM Processor Data Book
200
www..com
Signal Descriptions 30361D
SDA[12:0] SDBA[1:0] SDD[31:0] SDQM[3:0]# SDRAS# SDCAS# SDWE# SDCLK[2:0] SDCS[2:0]# SDCKE# SMROMCKE (GPIO[6]) RAD[31:0] RD[31:0] RBE[3:0]# RWE# ROE# RCS[3:0]# EWAIT# PREG# PCE[2:1]# POE# PWE# PIOR# PIOW# PWAIT# PIOS16# LCLK LWAIT# LRD[1:0]# LWR[1:0]#
UART0 SDRAM Controller
UART3
AU1500TM Processor
MAC0
PCMCIA
Static Bus Controller
U0TXD (GPIO[20]) U0RXD U3TXD (GPIO[23]) U3RXD U3CTS# (GPIO[9]) U3DSR# (GPIO[10]) U3DCD# (GPIO[11]) U3RI# (GPIO[12]) U3RTS# (GPIO[13]) U3DTR# (GPIO[14]) N0TXCLK N0TXEN N0TXD[3:0] N0RXCLK N0RXDV N0RXD[3:0] N0CRS N0COL N0MDC N0MDIO N1TXCLK N1TXEN (GPIO[24]) N1TXD[3:0] (GPIO[28:25]) N1RXCLK N1RXDV N1RXD[3:0] N1CRS N1COL N1MDC N1MDIO ACSYNC ACBCLK ACDO ACDI ACRST#
MII
MAC1
MII
LCD
USBH1P USBH1M USBH0P (USBDP) USBH0M (USBDM) USBDP (USBH0P) USBDM (USBH0M) PCI_AD[31:0] PCI_CBE[3:0]# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PERR# PCI_SERR# PCI_PAR PCI_DEVSEL# PCI_IDSEL PCI_LOCK# PCI_REQ[3:0]# PCI_GNT[3:0]# PCI_INT[A:D]# PCI_RST# PCI_CLK PCI_RSTO# (GPIO[200]) PCI_CFG PCI_CLKO GPIO[215:200] GPIO[28:23, 20, 15:0]
AC97 USB Host USB Device Clocks & Reset
AC Link
EXTCLK[1:0] (GPIO[3:2]) XTI12 XTO12 XTI32 XTO32 RESETIN# RESETOUT# ROMSEL ROMSIZE PWR_EN VDDXOK TRST# TDI TDO TMS TCK TC[3:0] TESTEN
PCI Interface
Power Mgmt. PCI Test & Debug
EJTAG
DMA
DMA_REQ0 (GPIO[4]) DMA_REQ1 (GPIO[5]) DMA_REQ2 (GPIO[208]) DMA_REQ3 (GPIO[209])
DMA REQs
GPIO2 GPIO
Power
VDDI[13:0], VDDX[39:0], VSS[55:0] XPWR12, XAGND12 XPWR32, XAGND32
Figure 11-1. External Signals
AMD AlchemyTM AU1500TM Processor Data Book
201
www..com
30361D Signal Descriptions
Table 11-3 on page 203 gives a description of all external signals on the AU1500 processor. The signals have been grouped by functional block. Signals that require external termination are noted in the description. Table 11-3 also defines the default state of the signals during a hardware reset, a runtime reset, and Sleep. The abbreviations used for the signal types and the signal states are defined in Table 11-1 and Table 11-2.
Table 11-1. Signal Type Abbreviations for Table 11-3
Signal Type I O I/O Z P G Definition Input. Note that all unused input pins should be terminated low or high via direct connection to either ground or power. Output Bidirectional Tristatable Power Ground
Table 11-2. Signal State Abbreviations for Table 11-3
Signal State 0 1 IN LV HIZ ON DEP UN NC NA Definition Driven low Driven high Signal is a input. If driven, an output signal continues to be driven at the last value before a reset or entering Sleep. TRI-STATE mode Clock remains on if already enabled. Depends (Signal-specific explanations are provided in table footnotes.) Unpredictable Not connected Does not apply because this signal is not the default function coming out of a hardware or runtime reset.
Note for Table 11-3 that the signal states shown in the far-right column are valid during Sleep. When waking from Sleep, the processor performs an internal system reset that produces the same signal behavior as a runtime reset with two exceptions: * SDRAM interface behavior. During and after a runtime reset the SDRAM configuration mode registers retain their values to allow a transaction in progress to complete; the remaining SDRAM configuration registers revert to their default values. Waking from Sleep, however, all SDRAM configuration registers revert to their default values, and the interface behaves the same as when coming out of a hardware reset. * PWR_EN behavior. During a runtime reset PWR_EN remains asserted. During Sleep, PWR_EN is negated. Waking from Sleep, PWR_EN is asserted according to the timing specified inSection 8.4.4.1 "Sleep Sequence and Timing" on page 174.
202
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
.
Table 11-3. Signal Description
Reset Run Time During Sleep
Signal SDRAM Interface SDA[12:0]
Type
Description
HW
O
Address Outputs: A0-A12 are sampled during the command (row-address A0-A12) and READ/ WRITE command to select one location out of the memory array in the respective bank. The address outputs also provide the opcode during a LOAD MODE REGISTER command.
ACTIVE
UN
UN
LV
SDBA[1:0]
O
Bank Address Outputs: SDBA1 and SDBA0 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. SDRAM Data Bus. During a hardware reset the SDRAM data bus cycles from low voltage to hi-Z and then low as follows: 0 after VDDXOK is asserted. In TRI-STATE when VDDI is on and RESETOUT# is asserted. 0 after hardware reset sequence is complete.
UN
UN
LV
SDD[31:0]
I/O
(See description at left.)
HIZ
LV
SDQM[3:0]#
O
Input/Output Mask: SDQM# is an input mask signal for write accesses and an output enable signal for read accesses. SDQM0# masks SDD[7:0]. SDQM1# masks SDD[15:8]. SDQM2# masks SDD[23:16]. SDQM3# masks SDD[31:24].
1
1
LV
SDRAS# SDCAS# SDWE# SDCLK[2:0]
O O O O
Command Outputs. SDRAS#, SDCAS#, and SDWE# (along with SDCSn#) define the command being sent to the SDRAM rank. Clock output corresponding to each of the three chip selects. Clock speed is 1/2 System Bus (SBUS) frequency when corresponding SDCSn# is set to SDRAM, 1/4 SBUS frequency when corresponding SDCSn# is set to SMROM. Programmable chip selects. Clock enable for SDRAM. Synchronous Mask ROM Clock Enable. Valid only when ROMSEL=1 and ROMSIZE=0. Must be pulled high if the system is booting from SMROM. Muxed with GPIO[6]. If ROMSEL and ROMSIZE are configured to boot from synchronous mask ROM, the SMROMCKE signal is selected for the pin coming out of reset; otherwise, GPIO[6] is selected.
1 1 1 0
1 1 1 ON
LV LV LV LV LV
SDCS[2:0]# SDCKE SMROMCKE
O O O
1 0 1
1 1 1
LV LV LV
AMD AlchemyTM AU1500TM Processor Data Book
203
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time During Sleep
Signal
Type
Description
HW
Static Bus (SRAM/IO/PCMCIA/Flash/ROM/LCD) Interface - Common Signals RAD[31:0] RD[31:0] RBE[3:0]# O I/O O Address Bus. Data Bus. Byte Enable. RBE0# corresponds to RD[7:0], RBE1# corresponds to RD[15:8], RBE2# corresponds to RD[23:16], RBE3# corresponds to RD[31:24]. Write Enable. Output Enable. Programmable Chip Selects. RCSn# is not used when configured as a PCMCIA device. Can be used to stretch the bus access time when enabled. This input is not recognized for chip selects configured as LCD or PCMCIA because these buses have their own wait mechanisms. UN 0 1 UN UN 1 LV LV LV
RWE# ROE# RCS[3:0]# EWAIT#
O O O I
1 1 1 IN
1 1 1 IN
LV LV LV LV
PCMCIA PREG# PCE[2:1]# POE# PWE# PIOR# PIOW# PWAIT# O O O O O O I Register-Only Access Signal. Card Enables. Output Enable. Write Enable. Read Cycle Indication. Write Cycle Indication. Extend Cycle. Note that this signal should be tied high through a resistor when the PCMCIA interface is not used. 16-bit Port Select. Note that this signal should be tied high through a resistor when the PCMCIA interface is not used. 1 1 1 1 1 1 IN 1 1 1 1 1 1 IN LV LV LV LV LV LV LV
PIOS16#
I
IN
IN
LV
LCD Controller Chip Interface LCLK LWAIT# LRD[1:0]# LWR[1:0]# O I O O Interface Clock. Extend Cycle. Note that this signal should be tied high through a resistor when not used. Read Indicators. Write Indicators. 0 IN 1 1 0 IN 1 1 LV LV LV LV
PCI Bus and Configuration PCI_AD[31:0] PCI_CBE[3:0]# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PERR# I/O I/O I/O I/O I/O I/O I/O PCI Address/Data. PCI Bus Command and Byte Enables. PCI Cycle Frame. PCI Initiator Ready. PCI Target Ready. PCI Target Stop. PCI Parity Error. Z Z Z Z Z Z Z Z Z Z Z Z Z Z LV LV LV LV LV LV LV
204
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
Table 11-3. Signal Description (Continued)
Reset Run Time Z Z Z IN Z IN 1 IN ON During Sleep LV LV LV LV LV LV LV LV LV
Signal PCI_SERR# PCI_PAR PCI_DEVSEL# PCI_IDSEL PCI_LOCK# PCI_REQ[3:0]# PCI_GNT[3:0]# PCI_INT[A:D]# PCI_CLKO
Type O I/O I/O I I/O I O I/O O
Description PCI System Error. PCI Parity. PCI Device Select. PCI Initialization Device Select Input. PCI Lock for Atomic Operations. PCI Arbiter Bus Request Inputs. PCI Arbiter Bus Grant Outputs. PCI Interrupts. PCI Clock Output. Note: Requires an external 22- series resistor placed within 0.5 inches of the part.
HW Z Z Z IN Z IN HIZ IN 0
PCI_CLK
I
PCI Input Clock. Note: Should be tied low through a resistor when the PCI bus is not used.
IN
IN
LV
PCI_RST#
I
PCI reset input Note: Should be tied low through a resistor when the PCI bus is not used.
IN
IN
LV
PCI_RSTO# (GPIO[200])
O
PCI Reset Output. Unlike other GPIOs, GPIO[200] defaults as an output with a zero voltage level coming out of reset. For this reason, GPIO[200] can be controlled by system software to act as a PCI reset output signal (labeled PCI_RSTO#) if needed. Note: Should be tied low through a pull-down resistor.
HIZ
0
LV
PCI_CFG
I
PCI configuration. Determines the mode (satellite or host) for the PCI interface at hardware reset. For satellite mode, tie PCI_CFG low. For host mode, tie PCI_CFG high. Note that PCI_CFG must not change state after system power up.
IN
IN
LV
USB Host USBH1P I/O Positive signal of differential USB host port 1 driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: USBH1M I/O Requires an external 27 ohm series resistor placed within 0.5 inches of the part. IN IN LV IN IN LV
Negative Signal of Differential USB Host Port 1 Driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: Requires an external 27 ohm series resistor placed within 0.5 inches of the part.
AMD AlchemyTM AU1500TM Processor Data Book
205
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time NA During Sleep LV
Signal USBH0P
Type I/O
Description Positive Signal of Differential USB Host Port 0 Driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: Requires an external 27ohm series resistor placed within 0.5 inches of the part.
HW NA
Muxed with USBDP. USBDP is the default signal coming out of hardware reset, runtime reset, and Sleep. USBH0M I/O Negative Signal of Differential USB Host Port 0 Driver. Requires an external 15 kohm pull-down resistor and ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: Requires an external 27 ohm series resistor placed within 0.5 inches of the part. NA NA LV
Muxed with USBDM. USBDM is the default signal coming out of hardware reset, runtime reset, and Sleep. USB Device USBDP I/O Positive Signal of Differential USB Device Driver. Requires a 1.5 kohm pull-up resistor to denote a full speed device. Also requires an external ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: Requires an external 27 ohm series resistor placed within 0.5 inches of the part. IN IN LV
Muxed with USBH0P. USBDP is the default signal coming out of hardware reset, runtime reset, and Sleep. USBDM I/O Negative Signal of Differential USB Device Driver. Requires an external ESD protection diode (transient voltage suppressor) to be USB 1.1 compliant. Note: Requires an external 27 ohm series resistor placed within 0.5 inches of the part. IN IN LV
Muxed with USBH0M. USBDM is the default signal coming out of hardware reset, runtime reset, and Sleep. UART0 U0TXD O UART0 Transmit. Muxed with GPIO[20]. GPIO[20] is the default signal coming out of hardware reset, runtime reset, and Sleep. UART0 Receive. NA NA LV
U0RXD
I
IN
IN
IN
206
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
Table 11-3. Signal Description (Continued)
Reset Run Time During Sleep
Signal UART3 U3TXD
Type
Description
HW
O
UART3 Transmit. Muxed with GPIO[23]. GPIO[23] is the default signal coming out of hardware reset, runtime reset, and Sleep. UART3 Receive. Clear to Send. Muxed with GPIO[9]. GPIO[9] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
NA
NA
LV
U3RXD U3CTS#
I I
IN NA
IN NA
LV LV
U3DSR#
I
Data Set Ready. Muxed with GPIO[10]. GPIO[10] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
NA
NA
LV
U3DCD#
I
Data Carrier Detect. Muxed with GPIO[11]. GPIO[11] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
NA
NA
LV
U3RI#
I
Ring Indication. Muxed with GPIO[12]. GPIO[12] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
NA
NA
LV
U3RTS#
O
Request to Send. Muxed with GPIO[13]. GPIO[13] is the default signal coming out of hardware reset, runtime reset, and Sleep.
NA
NA
LV
AMD AlchemyTM AU1500TM Processor Data Book
207
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time NA During Sleep LV
Signal U3DTR#
Type O
Description Data Terminal Ready. Muxed with GPIO[14]. GPIO[14] is the default signal coming out of hardware reset, runtime reset, and Sleep.
HW NA
Ethernet Controller 0 N0TXCLK I Continuous clock input for synchronization of transmit data. 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Indicates that the data nibble on N0TXD[3:0] is valid. Nibble wide data bus synchronous to N0TXCLK. For each N0TXCLK period in which N0TXEN is asserted, TXD[3:0] will have the data to be accepted by the PHY. While N0TXEN is de-asserted the data presented on TXD[3:0] should be ignored. Continuous clock that provides the timing reference for the data transfer from the PHY to the MAC. N0RXCLK is sourced by the PHY. The N0RXCLK shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). Indicates that a receive frame is in process and that the data on N0RXD[3:0] is valid. RXD[3:0] is a nibble wide data bus driven by the PHY to the MAC synchronous with N0RXCLK. For each N0RXCLK period in which N0RXDV is asserted, RXD[3:0] will transfer four bits of recovered data from the PHY to the MAC. While N0RXDV is de-asserted, RXD[3:0] will have no effect on the MAC. N0CRS shall be asserted by the PHY when either transmit or receive medium is non Idle. N0CRS shall be deasserted by the PHY when both the transmit and receive medium are Idle. N0CRS is an asynchronous input. N0COL shall be asserted by the PHY upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. N0COL is an asynchronous input. The N0COL signal is ignored by the MAC when operating in the full duplex mode. N0MDC is sourced by the MAC to the PHY as the timing reference for transfer of information on the N0MDIO signal. N0MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for N0MDC will be 160 ns each, and the minimum period for N0MDC will be 400 ns. N0MDIO is the bidirectional data signal between the MAC and the PHY that is clocked by N0MDC. IN IN LV
N0TXEN N0TXD[3:0]
O O
0 0
UN UN
LV LV
N0RXCLK
I
IN
IN
LV
N0RXDV N0RXD[3:0]
I I
IN IN
IN IN
LV LV
N0CRS
I
IN
IN
LV
N0COL
I
IN
IN
LV
N0MDC
O
0
UN
LV
N0MDIO
I/O
HIZ
UN
LV
208
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
Table 11-3. Signal Description (Continued)
Reset Run Time During Sleep
Signal Ethernet Controller 1 N1TXCLK
Type
Description
HW
I
Continuous clock input for synchronization of transmit data. 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Indicates that the data nibble on N1TXD[3:0] is valid. Muxed with GPIO[24]. GPIO[24] is the default signal coming out of hardware reset, runtime reset, and Sleep. Nibble wide data bus synchronous to N1TXCLK. For each N1TXCLK period in which N1TXEN is asserted, TXD[3:0] will have the data to be accepted by the PHY. While N1TXEN is de-asserted the data presented on TXD[3:0] should be ignored. Muxed with GPIO[28:25]. GPIO[28:25] are the default signals coming out of hardware reset, runtime reset, and Sleep.
IN
IN
LV
N1TXEN
O
NA
NA
LV
N1TXD[3:0]
O
NA
NA
LV
N1RXCLK
I
Continuous clock that provides the timing reference for the data transfer from the PHY to the MAC. N1RXCLK is sourced by the PHY. The N1RXCLK shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). Indicates that a receive frame is in process and that the data on N1RXD[3:0] is valid. RXD[3:0] is a nibble wide data bus driven by the PHY to the MAC synchronous with N1RXCLK. For each N1RXCLK period in which N1RXDV is asserted, RXD[3:0] will transfer four bits of recovered data from the PHY to the MAC. While N1RXDV is de-asserted, RXD[3:0] will have no effect on the MAC. N1CRS shall be asserted by the PHY when either transmit or receive medium is non Idle. N1CRS shall be deasserted by the PHY when both the transmit and receive medium are Idle. N1CRS is an asynchronous input. N1COL shall be asserted by the PHY upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. N1COL is an asynchronous input. The N1COL signal is ignored by the MAC when operating in the full duplex mode. N1MDC is sourced by the MAC to the PHY as the timing reference for transfer of information on the N1MDIO signal. N1MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for N1MDC will be 160 ns each, and the minimum period for N1MDC will be 400 ns. N1MDIO is the bidirectional data signal between the MAC and the PHY that is clocked by N1MDC.
IN
IN
LV
N1RXDV N1RXD[3:0]
I I
IN IN
IN IN
LV LV
N1CRS
I
IN
IN
LV
N1COL
I
IN
IN
LV
N1MDC
O
0
UN
LV
N1MDIO
I/O
0
UN
LV
AMD AlchemyTM AU1500TM Processor Data Book
209
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time During Sleep
Signal AC-Link ACSYNC ACBCLK ACDO ACDI ACRST# EJTAG TRST# TDI TDO
Type
Description
HW
O I O I O
Fixed Rate Sample Sync. Serial Data Clock. TDM Output Stream. TDM Input Stream. Codec Reset.
0 IN 0 IN 1
0 IN 0 IN 0
LV LV LV LV LV
I I O
Asynchronous TAP Reset. Test Data Input to the instruction or selected data registers. Sampled on the rising edge of TCK. Test Data Output from the instruction or data register. Transitions occur on the falling edge (valid on rising edge) of TCK. Control signal for TAP controller. Sampled on the rising edge of TCK. Control clock for updating TAP controller and shifting data through instruction or selected data register.
IN IN HIZ
IN IN UN
LV LV LV
TMS TCK Test TC[3:0] TESTEN GPIO GPIO[1:0] GPIO[3:2]
IOZ IOZ
I I
IN IN
IN IN
LV LV
I I
Test Clock Inputs (not used in typical application). Should be pulled low for normal operation. Test Enable (not used in typical applications). Should be pulled low for normal operation.
IN IN
IN IN
LV LV
General Purpose I/O. General Purpose I/O. Muxed with EXTCLK[1:0]. GPIO[3:2] are the default signals coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O. Can be configured as DMA_REQ0. General Purpose I/O. Can be configured as DMA_REQ1. General Purpose I/O. Muxed with SMROMCKE. If ROMSEL and ROMSIZE are configured to boot from synchronous mask ROM, the SMROMCKE signal is selected for the pin coming out of reset; otherwise, GPIO[6] is selected. General Purpose I/O. General Purpose I/O.
HIZ HIZ
DEP (Note 1) DEP (Note 1) DEP (Note 1) DEP (Note 1) DEP (Note 1)
LV LV
GPIO[4] GPIO[5] GPIO[6]
IOZ IOZ IOZ
HIZ HIZ HIZ
LV LV LV
GPIO[7] GPIO[8]
IOZ IOZ
HIZ HIZ
DEP (Note 1) DEP (Note 1)
LV LV
210
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
Table 11-3. Signal Description (Continued)
Reset Run Time DEP (Note 1) During Sleep LV
Signal GPIO[9]
Type IOZ
Description General Purpose I/O. Muxed with U3CTS#. GPIO[9] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
HW HIZ
GPIO[10]
IOZ
General Purpose I/O. Muxed with U3DSR#. GPIO[10] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
HIZ
DEP (Note 1)
LV
GPIO[11]
IOZ
General Purpose I/O. Muxed with U3DCD#. GPIO[11] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
HIZ
DEP (Note 1)
LV
GPIO[12]
IOZ
General Purpose I/O. Muxed with U3RI#. GPIO[12] is the default signal coming out of hardware reset, runtime reset, and Sleep. Note: For systems that use the UART3 interface without the optional modem control signals (sys_pinfunc[UR3]=0), the modem status interrupts must be disabled (uart3_inten[MIE]=0) to avoid false UART3 interrupts when using GPIO[9], GPIO[10], GPIO[11], or GPIO[12] as an input.
HIZ
DEP (Note 1)
LV
GPIO[13]
IOZ
General Purpose I/O. Muxed with U3RTS#. GPIO[13] is the default signal coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O. Muxed with U3DTR#. GPIO[14] is the default signal coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O.
HIZ
DEP (Note 1) DEP (Note 1) DEP (Note 1)
LV
GPIO[14]
IOZ
HIZ
LV
GPIO[15]
IOZ
HIZ
LV
AMD AlchemyTM AU1500TM Processor Data Book
211
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time DEP (Note 1) DEP (Note 1) DEP (Note 1) DEP (Note 1) 0 During Sleep LV
Signal GPIO[20]
Type IOZ
Description General Purpose I/O. Muxed with U0TXD. GPIO[20] is the default signal coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O. Muxed with U3TXD. GPIO[23] is the default signal coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O. Muxed with N1TXEN. GPIO[24] is the default signal coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O. Muxed with N1TXD[3:0]. GPIO[28:25] are the default signals coming out of hardware reset, runtime reset, and Sleep. General Purpose I/O (secondary GPIO block). Unlike other GPIOs, GPIO[200] defaults as an output with a zero voltage level coming out of reset. For this reason, GPIO[200] can be controlled by system software to act as a PCI reset output signal (labeled PCI_RSTO#) if needed. Note: Should be tied low through a resistor.
HW HIZ
GPIO[23]
IOZ
HIZ
LV
GPIO[24]
IOZ
HIZ
LV
GPIO[28:25]
IOZ
HIZ
LV
GPIO[200]
IOZ
HIZ
LV
GPIO[207:201] GPIO[208] GPIO[209] GPIO[215:210] External Clocks EXTCLK[1:0]
IOZ IOZ IOZ IOZ
General Purpose I/O (secondary GPIO block). General Purpose I/O (secondary GPIO block). Can be configured as DMA_REQ2. General Purpose I/O (secondary GPIO block). Can be configured as DMA_REQ3. General Purpose I/O (secondary GPIO block).
HIZ HIZ HIZ HIZ
HIZ HIZ HIZ HIZ
LV LV LV LV
O
General Purpose External Clocks. Muxed with GPIO[3:2]. GPIO[3:2] are the default signals coming out of hardware reset, runtime reset, and Sleep.
NA
NA
LV
System DMA Requests DMA_REQ0 (GPIO[4]) DMA_REQ1 (GPIO[5]) DMA_REQ2 (GPIO[208]) DMA_REQ3 (GPIO[209]) I I I I GPIO[4] can be configured as an external, system DMA request input. GPIO[5] can be configured as an external, system DMA request input. GPIO[208] can be configured as an external, system DMA request input. GPIO[209] can be configured as an external, system DMA request input. HIZ HIZ HIZ HIZ HIZ HIZ HIZ HIZ LV LV LV LV
212
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
Table 11-3. Signal Description (Continued)
Reset Run Time During Sleep
Signal
Type
Description
HW
System Clocks and Reset XTI12 I Internally Compensated 12 MHz (typical) Crystal Input. Note: The termination depends on the application as follows:
Crystal--Connect crystal between XTI12 and XTO12. Overdriven--Connect to external 12 MHz clock source and drive complementary to XTO12. XTO12 O Internally compensated 12 MHz (typical) Crystal Output. Note: The termination depends on the application as follows:
Crystal--Connect crystal between XTI12 and XTO12. Overdriven--Connect to external 12 MHz clock source and drive complementary to XTI12. XTI32 I Internally Compensated 32.768 KHz (typical) Crystal Input Note: The termination depends on the application as follows:
Crystal--Connect crystal between XTI32 and XTO32. Overdriven--Connect to external 32.768 KHz clock source through a series 10 KOHM resistor and drive complementary to XTO32. Not used--Connect to VDDX. XTO32 O Internally compensated 32.768 KHz (typical) crystal output Note: The termination depends on the application as follows:
Crystal--Connect crystal between XTI32 and XTO32. Overdriven--Connect to external 32.768 KHz clock source through a series 10 Kohm resistor and drive complementary to XTI32. Not used--Connect to VDDX. RESETIN# RESETOUT# ROMSEL I O I CPU Reset Input. Buffered output of CPU reset input (RESETIN#). Determines if boot is from ROM or SMROM. ROMSEL should be terminated appropriately as these signals should not change during runtime. IN 0 IN IN 0 IN LV 0 LV
AMD AlchemyTM AU1500TM Processor Data Book
213
www..com
30361D Signal Descriptions
Table 11-3. Signal Description (Continued)
Reset Run Time IN During Sleep LV
Signal ROMSIZE
Type I
Description Latched at the rising edge of reset to determine if ROM width is 16 or 32 bits. ROMSIZE should be terminated appropriately as these signals should not change during runtime.
HW IN
Power Management PWR_EN VDDXOK Power/Ground VDDI P Internal Core Voltage. Note: Follow the power supply layout guidelines in Section 12.11.2 "Decoupling Recommendations" on page 235. O I Power Enable Output. This signal is intended to be used as the regulator enable for VDDI (core power). Input to signal that VDDX is stable. 1 IN 1 IN 0 LV
VDDX
P
External I/O voltage. Note: Follow the power supply layout guidelines in Section 12.11.2 "Decoupling Recommendations" on page 235.
VSS XPWR12
G P
Ground 12 MHz (typical) oscillator and PLL power. Note: Connect to VDDX through a 10 ohm resistor. In addition a 22 F capacitor in parallel with a 0.01 F capacitor should be placed from this pin to XAGND12.
XAGND12 XPWR32
G P
12 MHz (typical) oscillator and PLL ground. 32.768 KHz (typical) oscillator and PLL power. Because XPWR32 powers other circuitry also, it should be connected even if the oscillator is not used. Note: Connect to VDDX through a 10 ohm resistor. In addition a 22 F capacitor in parallel with a 0.01 F capacitor should be placed from this pin to XAGND32.
XAGND32
G
32.768 KHz (typical) oscillator and PLL ground
Note 1. Depends on sys_trioutrd and sys_outputset. During a runtime reset, sys_pinfunc returns to its default value, but the GPIO control registers sys_trioutrd and sys_outputset remain unchanged.
214
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Signal Descriptions 30361D
AMD AlchemyTM AU1500TM Processor Data Book
215
www..com
Electrical and Thermal Specifications 30361D
12.0Electrical and Thermal Specifications
This chapter provides preliminary electrical specifications for the AU1500 processor, including the following: * Absolute Maximum Ratings * Thermal Characteristics * DC Parameters * AC Parameters * Power-up, Reset, Sleep, and Idle Timing * External Clock Specifications * Crystal Specifications * System Design Considerations
12
Max 2 3.6 3.6 VDDX + 0.5 85 100 125 Unit V V V V C C C
12.1
Absolute Maximum Ratings
Table 12-1 shows the absolute maximum ratings for the AU1500 processor. These ratings are stress ratings, operating at or beyond these ratings for extended periods of time may result in damage to the AU1500 processor. Unless otherwise designated all voltages are relative to VSS.
Table 12-1. Absolute Maximum Ratings
Parameter VDDI VDDX XPWR12, XPWR32 VIN TCASE Commerical TCASE Industrial (333 MHz part only) TS Description Core Voltage I/O Voltage Oscillator Voltage Voltage Applied to Any Pin Package Operating Temperature Package Operating Temperature Storage Temperature Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 0 -40 -40
AMD AlchemyTM AU1500TM Processor Data Book
216
www..com
Electrical and Thermal Specifications 30361D
12.2
Undershoot
The minimum DC voltage on input or I/O pins is -0.5V. However, during voltage transitions, the device can tolerate undershoot to -2.0V for up to 20 ns, as shown in Figure 12-1.
20 ns 20 ns
VIL -0.5V -2.0V
20 ns
Allowed Voltages
Figure 12-1. Voltage Undershoot Tolerances for Input and I/O Pins
12.3
Overshoot
The maximum DC voltage on input or I/O pins is (VDDX + 0.5) V. However, during voltage transitions, the device can tolerate overshooting VDDX to (VDDX + 2.0) V for up to 20 ns, as shown in Figure 12-2.
20 ns
VDDX + 2.0V VDDX + 0.5V VDDX
20 ns 20 ns
Allowed Voltages
Figure 12-2. Voltage Overshoot Tolerances for Input and I/O Pins
12.4
Thermal Characteristics
Table 12-2 shows the thermal characteristics for the AU1500 processor.
Table 12-2. Thermal Characteristics with Changing Air Flow Conditions
Still Air (Note 1) 33.1 5.0 50 lfpm (Note 2) (0.25 m/s) 31.8 100 lfpm (0.5 m/s) 30.7 150 lfpm (0.75 m/s) 30.0 200 lfpm (1.0 m/s) 28.6
Parameter JA JT
Unit C/W C/W
Note 1. Measured without forced air--natural convection only. Note 2. Linear feet per minute.
AMD AlchemyTM AU1500TM Processor Data Book
217
w
w
w
.
D
30361D
a
t
a
S
h
e
e
t
4
U
.
c
Electrical and Thermal Specifications
12.5
DC Parameters
Table 12-3 shows the DC parameters for the AU1500 processor. Unless otherwise designated all voltages are relative to VSS. The operating requirements for the power supply voltages (VDDX and VDDI) are given in the sections describing the DC characteristics for the different operating frequencies, beginning with Table 12-4.
Table 12-3. DC Parameters
Parameter VIHX VILX VOHX @ 2 mA VOLX @ 2 mA II CIN (Note 1) IXPWR12 (Note 2) IXPWR32 (Note 2) Description Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Input Capacitance XPWR12 Current XPWR32 Current 5 1 1 3 3 0.8 * VDDX 0.2 * VDDX 5 Min 2.4 0.2 * VDDX Nominal Max Unit V V V V A pF mA mA
Note 1. This parameter is by design and not tested. Note 2. Does not apply during Sleep.
12.5.1
Power and Voltage for 333, 400, and 500 MHz Rated Parts
The tables that follow give the voltage and power parameters for the individual MHz rated parts.
Table 12-4. Voltage and Power Parameters for 333 MHz Part
Parameter VDDI VDDX, XPWR12, XPWR32 (Note 1) Power: VDDI Power: VDDX IDLE Power (Note 3) Sleep Current (VDDI = VSS) Min 1.4 3.0 Typ 1.5 3.3 340 60 176 50 Max 1.6 3.6 755 (Note 2) 290 (Note 2) Unit V V mW mW mW A
Note 1. XPWR12 and XPWR32 should be connected to VDDX. For a description of this circuit connection, see the entries for XPWR12 and XPWR32 in Table 11-3 "Signal Description" on page 203. Note 2. While the maximum power numbers should be used when specifying a regulator for a system, the numbers are well above the typical power consumption because none of the power-saving design features (such as IDLE, or the automatic SBUS divider) are enabled. Note that because the particular application software and external loading affect the power consumption on a given system design, certain conditions may exist which could cause the maximum power consumption to be different than shown. Note 3. IDLE power is the power measured when the processor core is in the IDLE0 state. (IDLE0 maintains cache coherency by snooping the SBUS; IDLE1 does not snoop the bus. Because caches are turned off during the IDLE1 state, IDLE1 consumes less power than IDLE0.) Typically the IDLE state is entered during an operating system's wait loop in which the core has no processes to run. While the processor core is in IDLE, clocks to the core are gated off; however, all registers retain their values, and the peripherals, DMA engine, and the interrupts remain active so that the system is still functional.
218
AMD AlchemyTM AU1500TM Processor Data Book
w
w
w
.
D
a
t
a
S
h
e
e
30361D
t
4
U
.
c
Electrical and Thermal Specifications
Table 12-5. Voltage and Power Parameters for 400 MHz Part
Parameter VDDI VDDX, XPWR12, XPWR32 (Note 1) Power: VDDI Power: VDDX IDLE Power (Note 3) Sleep Current (VDDI = VSS) Min 1.4 3.0 Typ 1.5 3.3 595 105 205 50 Max 1.6 3.6 870 (Note 2) 340 (Note 2) Unit V V mW mW mW A
Note 1. XPWR12 and XPWR32 should be connected to VDDX. For a description of this circuit connection, see the entries for XPWR12 and XPWR32 in Table 11-3 "Signal Description" on page 203. Note 2. While the maximum power numbers should be used when specifying a regulator for a system, the numbers are well above the typical power consumption because none of the power-saving design features (such as IDLE, or the automatic SBUS divider) are enabled. Note that because the particular application software and external loading affect the power consumption on a given system design, certain conditions may exist which could cause the maximum power consumption to be different than shown. Note 3. IDLE power is the power measured when the processor core is in the IDLE0 state. (IDLE0 maintains cache coherency by snooping the SBUS; IDLE1 does not snoop the bus. Because caches are turned off during the IDLE1 state, IDLE1 consumes less power than IDLE0.) Typically the IDLE state is entered during an operating system's wait loop in which the core has no processes to run. While the processor core is in IDLE, clocks to the core are gated off; however, all registers retain their values, and the peripherals, DMA engine, and the interrupts remain active so that the system is still functional.
Table 12-6. Voltage and Power Parameters for 500 MHz Part
Parameter VDDI VDDX, XPWR12, XPWR32 (Note 1) Power: VDDI Power: VDDX IDLE Power (Note 3) Sleep Current (VDDI = VSS) Min 1.71 3.0 Typ 1.8 3.3 1080 120 293 50 Max 1.89 3.6 1625 (Note 2) 450 (Note 2) Unit V V mW mW mW A
Note 1. XPWR12 and XPWR32 should be connected to VDDX. For a description of this circuit connection, see the entries for XPWR12 and XPWR32 in Table 11-3 "Signal Description" on page 203. Note 2. While the maximum power numbers should be used when specifying a regulator for a system, the numbers are well above the typical power consumption because none of the power-saving design features (such as IDLE, or the automatic SBUS divider) are enabled. Note that because the particular application software and external loading affect the power consumption on a given system design, certain conditions may exist which could cause the maximum power consumption to be different than shown. Note 3. IDLE power is the power measured when the processor core is in the IDLE0 state. (IDLE0 maintains cache coherency by snooping the SBUS; IDLE1 does not snoop the bus. Because caches are turned off during the IDLE1 state, IDLE1 consumes less power than IDLE0.) Typically the IDLE state is entered during an operating system's wait loop in which the core has no processes to run. While the processor core is in IDLE, clocks to the core are gated off; however, all registers retain their values, and the peripherals, DMA engine, and the interrupts remain active so that the system is still functional.
AMD AlchemyTM AU1500TM Processor Data Book
219
www..com
30361D Electrical and Thermal Specifications
12.6
AC Parameters
This section describes the AC parameters for I/O devices in the AU1500 processor. Each class of output signal has different capacitive loads. As the capacitance on the load increases the propagation delay will increase. These specifications assume the maximum capacitive load to be 50 pF for all I/O signals other than the SDRAM interface. The timing of those signals which have synchronous relationships or have a defined requirement are given. The timing diagrams are shown to illustrate the timing only and should not necessarily be interpreted as the functional timing of the port. It is assumed that the timing and/or functionality of the protocol related to the port is adhered to by the external system. The protocol timing is not necessarily presented here and the appropriate section or specification should be referenced for complete functional timing parameters. Timing measurements are made from 50% threshold to 50% threshold. Certain timing parameters are based off of the internal System Bus (SBUS) clock. When this is the case the symbol Tsys is used. Tsys is defined in nanoseconds as: Tsys = SD/CPU The symbol CPU should be interpreted as the CPU clock speed in MHz as set by the CPU PLL. See Section 8.1 "Clocks" on page 154 for details. The symbol SD is the SBUS divider. See Section 8.4 "Power Management" on page 172 for details.
220
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.6.1
SDRAM Timing and Loading
The SDRAM controller loading limits are as follows: * SDRAM outputs excluding the clocks and chip-selects can support a maximum capacitive load of 35 pF (six 5 pF gate loads and 5 pF representing the trace). * Each clock and each chip-select supports a maximum capacitive load of 15 pF (two 5 pF gate loads and 5 pF representing the trace). The SDRAM is a high speed interface. Reflection and propagation delays should be accounted for in the system design. As a general rule of thumb, unterminated etches should be kept to 6 inches or less.
Table 12-7. SDRAM Controller Interface
Signal SDCLKn SDCSn#, SDRAS#, SDCAS#, SDWE#, SDBA[1:0], SDA[12:0], SDQM[3:0]#, SDD[31:0] (output) SDD[31:0] (input) SDD[31:0] (input) Symbol Tsdclk Tsdd Parameter SDCLKn Clock Cycle Delay from SDCLKn Min 2 * Tsys Tsdclk/4 - 1.5 Tsdclk/4 + 2 Max Unit ns ns
Tsdsu Tsdh
Data setup to SDCLKn Data hold from SDCLKn
1.8 1.7
ns ns
Tsdclk Tsdsu SDCLKn SDCSn#, SDRAS#, SDCAS#, SDWE#, SDBA[1:0], SDA[12:0], SDQM[3:0#], SDD[31:0] (output) Tsdd
Tsdh SDD[31:0] (input)
Figure 12-3. SDRAM Timing
AMD AlchemyTM AU1500TM Processor Data Book
221
www..com
30361D Electrical and Thermal Specifications
12.6.2
Static Bus Controller Timing
The timing presented in registers mem_sttimen are not presented here. The parameters in these registers are presented in a certain number of clock cycles and are accurate to within 2 ns.
Table 12-8. Static RAM, I/O Device and Flash Timing
Signal RBE[3:0]#, ROE#, RAD[31:0], burstsize[2:0] RD[31:0] (read) Symbol Trcd Parameter Delay from RCSn#. Min -2 Max +2 Unit ns
Trsu
Data setup to RCSn#. Note that Trsu does not apply when EWAIT# is used to extend the cycle.
15
ns
RD[31:0] (read)
Trsue
Data setup to EWAIT#. Note that Trsue applies only when EWAIT# is used to extend the cycle. Data hold from RCSn#. Delay from RWE# to data out EWAIT# setup to RCSn# for reads, or RWE# for writes. If EWAIT# does not meet this setup time the cycle will not be held.
0
ns
RD[31:0] (read) RD[31:0] (write) EWAIT#
Trh Trod Trwsu
0 -2 3 * Tsys + 15 2
ns ns ns
RCS# (reads), RWE# (writes) burstsize[2:0]
Trwd Trbd
Delay from EWAIT#. Delay from RCSn#.
2 * Tsys
3 * Tsys + 15 Tsys + 2
Trwsu Trwd Trsu Trcd Trcd
RCSn# RBE[3:0#], ROE#, RAD[31:0] burstsize[2:0]
Trwsu Trwd Trod
Trcd
Trbd
RWE#
RD[31:0] (output) EWAIT#
Trsue Trh
RD[31:0] (input)
Figure 12-4. Static RAM, I/O Device and Flash Timing
222
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
Table 12-9. PCMCIA Timing
Signal PREG#, RAD[31:0], RD[31:0] (output) PIOS16# PIOS16# ROE# RD[15:0] (input) Symbol Tpcd Parameter Delay from PCEn# Min -2 Max +2 Unit ns
Tpios Tpioh Tpoed Tpsu
PIOS16# setup to PIOR#, PIOW# PIOS16# hold from PIOR#, PIOW# ROE# delay from POE#, PIOR# Data setup to POE#, PIOR#. Note that Tpsu does not apply when PWAIT# is used to extend the cycle. Data setup to PWAIT#. Note that Tpsup applies only when PWAIT# is used to extend the cycle. Data hold from POE#, PIOR# PWAIT# setup to POE#, PWE#, PIOR#, PIOW# If PWAIT# does not meet this setup time the cycle will not be held
4 * Tsys + 15 0 -2 Tsys + 15 +2
ns ns ns ns
RD[15:0] (input)
Tpsup
0
ns
RD[31:0] PWAIT#
Tph Tpwsu
0 4 * Tsys + 15
ns ns
POE#, PWE#, PIOR#, PIOW#
Tpwd
POE#, PWE#, PIOR#, PIOW# delay from PWAIT#.
3 * Tsys
4 * Tsys + 15
ns
PCEn# PREG#, RAD[31:0], RD[15:0] (output) PWE#, PIOW#
Tpios Tpcd Tpcd
Tpwsu Tpwd
POE#, PIOR#
Tpoed
Tpsu Tpcd
ROE#
Tpioh
PIOS16#
Tpsup
PWAIT#
Tph
RD[15:0] (input)
Figure 12-5. PCMCIA Host Adapter Timing
AMD AlchemyTM AU1500TM Processor Data Book
223
www..com
30361D Electrical and Thermal Specifications
Table 12-10. LCD Timing
Signal LCLK RCSn#, RAD[31:0], RD[15:0] (output) RD[15:0] (input) RD[15:0] (input) LWAIT# Symbol Tlclk Tlcd Tlsu Tlh Tlwsu Parameter LCLK Period. This parameter is programmed in mem_stcfg0[D5]. Delay from LCLK Data setup to LRDn# Data hold from LRDn# LWAIT# setup to LRDn# for reads, or LWRn# for writes. If LWAIT# does not meet this setup time the cycle will not be held. LRDn# (reads), LWRn# (writes) Tlwd Delay from LWAIT# 2 * Tsys 3 * Tsys + Tlclk + 15 ns Min Tsys * 4 -2 15 0 3 * Tsys + Tlclk + 15 Max Tsys * 5 2 Unit ns ns ns ns ns
Tlclk
LCLK RCSn# RAD[31:0], RD[15:0] (output) LWRn#
Tlsu Tlcd Tlcd
Tlwsu Tlwd
LRDn#
LWAIT#
Tlh
RD[15:0] (input)
Figure 12-6. LCD Interface Timing
224
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.6.3
PCI Timing and Loading
The PCI controller conforms to the PCI 2.2 Local Bus Specification for both the 33 MHz and 66 MHz options. The timing shown in Table 12-11 assumes a maximum of four PCI loads with each slot counting as one load. Trace lengths of PCI signals should be kept to a maximum of 9 inches.
Table 12-11. PCI Controller Interface
66 MHz Signal PCI_CLK All outputs All inputs Symbol Tpclk Tpcd Tpsu Tpdh Parameter PCI_CLK clock cycle Delay from PCI_CLK Data setup to PCI_CLK Data hold from PCI_CLK Min 15 2 3 0 Max 30 6 Min 30 2 7 0 33 MHz Max * 11 Unit ns ns ns ns
Tpclk Tpsu PCI_CLK Tpcd All outputs Tpdh All inputs
Figure 12-7. PCI Timing
AMD AlchemyTM AU1500TM Processor Data Book
225
www..com
30361D Electrical and Thermal Specifications
12.6.4 12.6.5
GPIO Input Timing Requirements GPIO Input Edge Rate
For level-sensitive GPIO inputs, edge rates as slow as 5 ms can be used. Note that no hysteresis is used on the inputs so for edge-sensitive inputs (such as clocks and edge-triggered interrupts) use a 20-ns (or faster) edge rate to ensure that noise does not cause false edges as the signal transitions through the threshold region.
12.6.6
GPIO Interrupt Timing
For system designs using GPIO signals as level-triggered interrupts, the signal level must be stable for at least 10 ns in order for a signal state change to be detected. See Table 12-12 and Figure 12-8.
Table 12-12. GPIO Timing for Interrupts
Signal GPIO[n] Symbol Tmin Parameter Minimum high or low time for interrupt. The level is programmable. This timing reflects the minimum active period for the level programmed. Min 10 Max Unit ns
Tmin
GPIO[n]
Figure 12-8. GPIO Interrupt Timing
226
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.6.7
Peripheral Timing
This section contains the electrical timing specifications for the integrated peripherals. 12.6.7.1 Ethernet MII Timing
Table 12-13. Ethernet MII Timing
Signal N0TXCLK, N0RXCLK, N1TXCLK, N1RXCLK Symbol Teth Parameter Ethernet transmit/receive clock cycle time (25% of data rate) Ethernet transmit/ receive clock duty cycle N0TXEN, N0TXD[3:0], N1TXEN, N1TXD[3:0] N0RXD[3:0], N0RXDV N1RXD[3:0], N1RXDV Ted Delay from TXCLK to TXEN, TXD[3:0] Min Max Unit ns % ns
40 100ppm (100 Mbps) 400 100ppm (10 Mbps) 35 0 65 25
Tesu Teh
Setup time before RXCCLK for RXD, and RXDV Hold time from RXCLK for RXD, and RXDV MDC cycle time MDC duty cycle
10 10 SBUS clock / 160 40 0 10 10 0 300 60 300
ns ns
N0MDC, N1MDC
Tmdc
% ns ns ns ns
N0MDIO, N1MDIO
Tmdd Tmsu Tmh Tmz
Delay from MDC to MDIO Setup time before MDC for MDIO Hold time from MDC for MDIO Delay from MDC to MDIO TRI-STATE Minimum active time
N0CRS, N0COL, N1CRS, N1COL
Ta
Teth
NnTXCLK
Ted
NnTXD[3:0], NnTXEN
Tesu Teth
NnRXCLK
Teh
NnRXD[3:0], NnRXDV
Tmdc
Tmsu
NnMDC
Tmz Tmdd Tmh
NnMDIO
Ta
NnCRS, NnCOL
Figure 12-9. Ethernet MII Timing Diagram
AMD AlchemyTM AU1500TM Processor Data Book 227
www..com
30361D Electrical and Thermal Specifications
12.6.7.2
AC97 Timing
Table 12-14. AC-Link Interface Timing
Signal ACBCLK Symbol Tabc Tabh Tabl ACSYNC Tacs Tacsh Tacsl ACSYNC ACDO ACDI Tad Tasu Tah Parameter AC97 bit clock cycle time AC97 bit clock high time AC97 bit clock low time AC97 sync cycle AC97 sync high time AC97 sync low time Delay from ACBCLK to ACSYNC and ACDO on output Setup before ACBCLK for ACDI Hold after ACBCLK for ACDI 10 10 Min Max Unit MHz ns ns KHz s s ns ns ns
12.288 (typical) 36 36 48 (typical) 1.3 (typical) 19.5 (typical) 15 45 45
Note:
ACRST# is an asynchronous signal controlled by software through the register ac97_config. It has no relationship to the other AC97 signals.
Tabc Tasu ACBCLK Tabl Tabh
Tad ACSYNC
Tad ACDO Tah ACDI Tacs Tacsh Tacsl ACSYNC
Figure 12-10. AC-Link Timing Diagram
228
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.6.7.3
EJTAG Interface Timing
Table 12-15. EJTAG Interface Timing
Signal TCK Symbol Tec Tech Tecl TMS, TDI Tesu Teh TDO Teco Tecz TRST# Trstl Parameter EJTAG TCK cycle time TCK high time TCK low time Setup before TCK for TMS and TDI Hold after TCK for TMS and TDI Delay from TCK to TDO on output Delay from TCK to TDO TRI-STATE TRST# low time 25 Min 40 10 10 5 3 15 15 Max Unit ns ns ns ns ns ns ns ns
Tesu TCK Teh TMS, TDI
Tec
Tech
Tecl
Teco TDO Trstl TRST#
Tecz
Figure 12-11. EJTAG Timing Diagram
AMD AlchemyTM AU1500TM Processor Data Book
229
www..com
30361D Electrical and Thermal Specifications
12.7
Power-up and Reset Timing
This section provides the timing specifications for the power-up sequence, and the hardware and runtime reset sequences. (See Section 9.0 "Power-up, Reset and Boot" on page 180 for functional descriptions of the sequences.)
12.7.1
Power-up Sequence Timing Table 12-16. Power-up Timing Parameters
Parameter Tvo Tpen Tvi
Description VDDX at 90% of nominal to VDDXOK asserted VDDXOK asserted to PWR_EN driven high PWR_EN to VDDI stable
Min 0
Max
Unit ns
30 20
ns ms
VDDX Tvo VDDXOK Tpen PWR_EN Tvi VDDI
Figure 12-12. Power-up Sequence
230
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.7.2
Hardware Reset Timing Table 12-17. Hardware Reset Timing Parameters
Parameter Tvxr Tvl Trstl Tvro
Description VDDXOK asserted to RESETIN# deasserted VDDXOK low time RESETIN# low time RESETIN# to RESETOUT# delay MAX = max[750 ns, 170 ms - Tvxr]
Min 0 ns 1 s 1 s 600 ns
Typ
Max System Dependent
See Description 135 ns 1 s
Trocs
RESETOUT# to RCS0#/SDCS0# asserted.
Tvl VDDXOK RESETIN# Tvro RESETOUT# Trocs RCS0#/SDCS0# Trstl Tvxr
Figure 12-13. Hardware Reset Sequence
AMD AlchemyTM AU1500TM Processor Data Book
231
www..com
30361D Electrical and Thermal Specifications
12.7.3
Runtime Reset Timing Table 12-18. Runtime Reset Timing Parameters
Parameter Trstl Trof
Description RESETIN# low time RESETIN# falling to RESETOUT# falling MAX: 25 ns + (0.5 * (CPU Clock/2))
Min 1 s
Typ
Max
See Description 120 CPU clocks 65 ns See Description 500 ns
Tror
RESETIN# rising to RESETOUT# rising MAX: 25 ns + (0.5 * (CPU Clock/2)) + (120 * CPU Clock)
Trocs
RESETOUT# to RCS0#/SDCS0# asserted. Note that the timing values shown assume a 400 MHz CPU clock.
VDDX (at nominal voltage) VDDXOK (asserted high) PWR_EN (remains asserted) VDDI (at nominal voltage) Trstl RESETIN# RESETOUT# Trof Tror
Trocs RCS0#/SDCS0#
Figure 12-14. Runtime Reset Sequence
232
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.8
Asynchronous Signals
GPIO The GPIO signals are driven by software. Note, however, when GPIO signals are used as inputs, there are timing requirements to ensure signal state changes are recognized cleanly; see Section 12.6.4 "GPIO Input Timing Requirements" on page 226. UART All UART signals are asynchronous to other external signals. USB All USB signals are asynchronous to other external signals. The USB protocol should be followed for appropriate operation.
12.9
External Clock Specifications
The EXTCLK[1:0] external clocks have a maximum frequency rating of (Fmax / 16), where Fmax is the maximum frequency rating for the part. Table 12-19 provides the EXTCLK[1:0] specifications.
Table 12-19. External Clock EXTCLK[1:0] Specifications
333 MHz Specification Frequency Frequency jitter Duty cycle 40 Min Max 20.81 4 60 40 400 MHz Min Max 25 4 60 40 500 MHz Min Max 31.25 4 60 Unit MHz % %
AMD AlchemyTM AU1500TM Processor Data Book
233
www..com
30361D Electrical and Thermal Specifications
12.10 Crystal Specifications
Note that load capacitors for the external oscillators are integrated into the AU1500 processor so no external circuitry is required when using the specified crystal. For design layout considerations concerning the crystals, see Section 12.11.1 "Crystal Layout" on page 235. Table 12-20 provides the specification for the parallel resonant 12 MHz crystal to be placed between XTI12 and XTO12. Table 12-21 provides the specification for the parallel resonant 32 KHz crystal to be placed between XTI32 and XTO32.
Table 12-20. 12 MHz Crystal Specification
Specification Resonant Frequency Frequency Stability Motional Resistance Shunt Capacitance Load Capacitance (Note 1) Drive Level Crystal Type Note 1. This capacitance is integrated on the AU1500. AT Cut 8 <5 12 Min 11 Typ 12 Max 15 100 60 7 20 100 Unit MHz ppm Ohms pF pF W
Table 12-21. 32.768 KHz Crystal Specification
Specification Resonant Frequency Equivalent Series Resistance Shunt Capacitance Load Capacitance (Note 1) Motional Capacitance Drive Level Quality Factor Crystal Type Note 1. This capacitance is integrated on the AU1500. 40k Tuning Fork 6 3 1.5 Min Typ 32.768 50k 2.0 12 4 1 Max Unit KHz Ohms pF pF fF W
234
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Electrical and Thermal Specifications 30361D
12.11 System Design Considerations
This section provides information for system-level design issues.
12.11.1 Crystal Layout
The crystal layouts are critical. Without using vias, place traces directly over a ground plane on the top layer with keep-outs on all surrounding sides. Trace lengths should be less than 0.5 inches, and trace widths should be set to the minimum signal trace width for the design. Be sure not to allow other signals to come within 0.025 inches of these sensitive analog signals.
12.11.2 Decoupling Recommendations
This section provides recommendations for minimizing noise in a system. Note that specific decoupling requirements are system dependent. To filter noise on the power supplies, VDDX and VDDI, as well as XPWR12 and XPWR32, should be bypassed to ground using 10 F capacitors: For each of the four sides of the package, place a capacitor within 0.5 inches. To filter high-frequency noise, capacitors in the 10 nF range should be placed under the package: * For minimal high-frequency decoupling, use six to eight 10 nF capacitors. * For systems requiring a broader spectrum of high-frequency noise be filtered, use four 15 nF and four 6.8 nF capacitors.
AMD AlchemyTM AU1500TM Processor Data Book
235
www..com
30361D Electrical and Thermal Specifications
236
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
13.0Packaging, Pin Assignments, and Ordering Information
This chapter provides information about the AU1500 processor package and pin assignment, as well as providing ordering information. The contents of the chapter are organized as follows: * The package dimensions are shown in Figure 13-1 starting on page 238. The AU1500 is packaged in a 424-pin LF-PBGA device. * Figure 13-2 (starting on page 240) is the connection diagram showing the pin and signal placement on the package. For pins that provide multiple signal functions, the default signal is shown first followed by the alternate signal in parentheses. Note that the black square in the upper-left hand corner indicates where the device is keyed. * The pin assignment listing ordered by pin number starts on page 242. * The pin assignment listing sorted by default signal starts on page 248. * The pin assignment listing sorted by alternate signal starts on page 253. * Ordering information is supplied on page 254.
13
AMD AlchemyTM AU1500TM Processor Data Book
237
www..com
30361D Packaging, Pin Assignments, and Ordering Information
13.1
Packaging
19 A
PIN 1 I.D.
19
TOP VIEW
B
SIDE VIEW DETAIL K
NOTES 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 . 2. ALL DIMENSIONS ARE IN MILLIMETERS . 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. BALL DIAMETER IS MEASURED AT ITS MAXIMUM DIMENSION IN A PLANE PARALLEL TO DATUM C. 5. THIS PACKAGE IS DIMENSIONED IN THE MANNER OF JEDEC OUTLINE MO-205 REV E, VARIATION Ax.
Figure 13-1. Package Dimensions
238
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
17.6 0.8 A1 CORNER
0.8
17.6
424x O 0.4 +/- 0.05
O0.08 M C O0.15 M C A B
BOTTOM VIEW
4
0.97 MIN
1.45 MAX
0.10 C
0.25 MIN
SEATING PLANE
C
0.15 C
DETAIL K
Figure 13-1. Package Dimensions (Continued)
AMD AlchemyTM AU1500TM Processor Data Book
239
www..com
30361D Packaging, Pin Assignments, and Ordering Information
13.2
Pin Assignment
Figure 13-2. Connection Diagram--Top View
1 2 XTO32 3 XTI32 4 XTO12 5 XTI12 6 RESETIN# VDDX TC0 7 GPIO[2] (EXTCLK0) VSS TC1 GPIO[3] (EXTCLK1) 8 GPIO[4] (DMA_REQ0) GPIO[5] (DMA_REQ1) TC2 9 PIOR# 10 PREG# 11 PCE2# 12 EWAIT#
A
B
TESTEN
XPWR32 VSS VDDX SDA4 VSS VDDX SDBA0
XAGND32
XPWR12
XAGND12
POE#
PCE1#
LWAIT#
RD1
C
SDA8
TMS
VDDXOK
ROMSEL
PIOW# GPIO[6] (SMROMCKE)
PWE#
LRD0#
LWR1#
D
SDA7
RESETOUT#
TRST#
ROMSIZE
GPIO[1]
TC3
GPIO[7]
LRD1#
LCLK
E
SDA3
SDA11
SDA12
PWR_EN
GPIO[0] VDDX VDDX VDDX SDCS2# VDDX VDDI VDDI SDD17 VDDI VDDX VDDX VSS VSS VSS VSS VSS VDDX VDDX VSS VSS VSS VSS VSS VSS VSS VDDX VDDI VSS VSS VSS VSS VSS VSS VSS VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VDDI VDDX
F
SDA2
SDA9
SDA10
SDA6
PIOS16#
PWAIT#
LWR0#
G
SDBA1
SDA5
SDA0
H
SDQM3#
SDA1
SDQM2#
J
SDCKE
SDCAS#
SDQM0#
SDQM1#
K
SDWE#
SDRAS#
SDCLK2
SDCLK1
SDD31
L
SDCS0#
SDCS1#
SDD30
SDD27
SDD25
M
SDD28
SDD29
SDD26
SDCLK0
N
SDD24
SDD23
SDD22
SDD21
P
SDD20
SDD19
SDD16
SDD15
SDD12 VDDX VDDX VDDX SDD1 GPIO[208] (DMA_REQ2) GPIO[212] GPIO[210] VDDX
R
SDD18
SDD14 VSS VDDX SDD4
SDD11
SDD8
T
SDD13
SDD9
SDD7
U
SDD10
SDD5 GPIO[14] (U3DTR#) ACRST# GPIO[11] (U3DCD#) GPIO[8] VDDX GPIO[213] 3
GPIO[15]
V
SDD6
SDD0
VDDX
GPIO[27] (N1TXD2)
N1CRS
N0COL
W
SDD3 GPIO[13] (U3RTS#) ACSYNC
SDD2
GPIO[214]
GPIO[211] GPIO[12] (U3RI#) TDI
Y
ACDO
GPIO[215] GPIO[209] (DMA_REQ3) TDO
GPIO[28] (N1TXD3) TCK
GPIO[25] (N1TXD0) GPIO[26] (N1TXD1) GPIO[24] (N1TXEN) N0MDC 9
N0MDIO
N0TXD3
N0RXDV
AA
ACBCLK VSS
GPIO[207] VSS N1RXDV 6
GPIO[206] VDDX N1RXCLK 7
N1RXD1
N0TXD1
N0TXEN
AB
ACDI
N1COL
N1RXD3
N1RXD0
N1TXCLK
GPIO[205]
AC
GPIO[10] GPIO[9] (U3DSR#) (U3CTS#) 1 2
N1MDIO 4
N1MDC 5
N1RXD2 8
N0TXD2 10
N0TXD0 11
GPIO[204] 12
240
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Figure 13-2.
13 RD2 14 RD6 15 RD8 16 RD17
Connection Diagram--Top View (Continued)
17 RD18 VDDX RD26 18 RD19 VSS RD27 19 RD23 20 RD24 21 RAD1 VDDX RAD2 22 RAD5 VSS RAD3 23 RAD8 A
RD3
RD7
RD12
RD14
RD25
RD30
RAD4
B
RD4
RD11
RD15
RD21
RD28
RAD0
RAD13
C
RD5
RD10
RD16
RD20
RD22
RD31
RAD7
RAD6
RAD15
RAD17
RAD18
D
RD29 VDDX VDDX VDDX VDDI VSS VSS VSS VSS VSS VSS VSS VDDI VDDX VSS VSS VSS VSS VSS VSS VSS VDDI VDDX VSS VSS VSS VSS VDDX VDDX VDDI VDDI VDDI VDDI VDDX PCI_REQ0# VDDX RBE2#
RAD10
RAD9
RAD11
RAD21 VDDX VSS RAD28
RAD22
E
RD0
RD9
RD13
RAD12
RAD14
RAD16
RAD23
F
RAD19
RAD20
RAD26
G
RAD25
RAD24
RAD27
H
RAD30
RAD29
RBE0#
RAD31
J
RCS2#
RWE#
RBE3#
RBE1#
ROE#
K
PCI_STOP#
U0RXD
RCS1#
RCS3# GPIO[23] (U3TXD) PCI_DEVSEL#
RCS0# GPIO[20] (U0TXD) U3RXD
L
PCI_FRAME#
PCI_IRDY#
M
PCI_CLKO
PCI_CLK
N
PCI_PAR
PCI_GNT1#
PCI_GNT0#
PCI_LOCK#
PCI_TRDY#
P
PCI_REQ3# VDDX VDDX
PCI_SERR#
PCI_CFG
PCI_REQ2#
PCI_REQ1#
R
PCI_AD4
PCI_AD3
PCI_GNT3# VDDX VSS PCI_AD2
PCI_GNT2#
T
PCI_AD10
PCI_AD8
PCI_PERR#
U
N0RXD3
N0RXD2
PCI_INTB#
VDDX
VDDX PCI_AD16
PCI_AD11
PCI_AD15
PCI_AD6
PCI_AD0
V
PCI_AD17 USBDP (USBH0P) PCI_AD22
USBH1M USBDM (USBH0M) PCI_AD20
PCI_AD5
PCI_AD1
W
N0RXCLK
GPIO[202]
PCI_INTC#
PCI_INTA#
PCI_AD25
PCI_AD21
PCI_AD13
PCI_AD9 VDDX VSS PCI_AD19 22
PCI_AD7
Y
GPIO[203]
GPIO[201]
PCI_CBE3#
PCI_CBE1#
PCI_AD31 VSS PCI_CBE0# 17
PCI_AD26 VDDX PCI_IDSEL 18
USBH1P
PCI_AD12
AA
N0RXD1
N0CRS
PCI_RST# GPIO[200] (PCI_RSTO#) 15
PCI_INTD#
PCI_AD29
PCI_AD27
PCI_AD23
PCI_AD14
AB
N0RXD0 13
N0TXCLK 14
PCI_CBE2# 16
PCI_AD30 19
PCI_AD28 20
PCI_AD24 21
PCI_AD18 23
AC
AMD AlchemyTM AU1500TM Processor Data Book
241
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-1. Pin Assignment -- Sorted by Pin Number
Pin No. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 Default Signal XTO32 XTI32 XTO12 XTI12 RESETIN# GPIO[2] GPIO[4] PIOR# PREG# PCE2# EWAIT# RD2 RD6 RD8 RD17 RD18 RD19 RD23 RD24 RAD1 RAD5 RAD8 TESTEN XPWR32 XAGND32 XPWR12 XAGND12 VDDX VSS GPIO[5] POE# PCE1# LWAIT# RD1 RD3 RD7 RD12 RD14 VDDX DMA_REQ1 EXTCLK0 DMA_REQ0 Alternate Signal Pin No. B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Default Signal VSS RD25 RD30 VDDX VSS RAD4 SDA8 VSS TMS VDDXOK ROMSEL TC0 TC1 TC2 PIOW# PWE# LRD0# LWR1# RD4 RD11 RD15 RD21 RD26 RD27 RD28 RAD0 RAD2 RAD3 RAD13 SDA7 VDDX RESETOUT# TRST# ROMSIZE GPIO[1] GPIO[3] TC3 GPIO[6] GPIO[7]
AMD AlchemyTM AU1500TM Processor Data Book
Alternate Signal
EXTCLK1
SMROMCKE
242
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-1.
Pin No. D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E5 E6 E18 E19 E20 E21 E22 E23 F1 F2 F3 F4 F5 F7 F8 F9 F10 F11 F13 F14 F15 F16 Default Signal LRD1# LCLK RD5 RD10 RD16 RD20 RD22 RD31 RAD7 RAD6 RAD15 RAD17 RAD18 SDA3 SDA4 SDA11 SDA12 PWR_EN GPIO[0] RD29 RAD10 RAD9 RAD11 RAD21 RAD22 SDA2 VSS SDA9 SDA10 SDA6 VDDX VDDX PIOS16# PWAIT# LWR0# RD0 RD9 RD13 VDDX
Pin Assignment -- Sorted by Pin Number (Continued)
Alternate Signal Pin No. F17 F19 F20 F21 F22 F23 G1 G2 G3 G4 G6 G18 G20 G21 G22 G23 H1 H2 H3 H4 H6 H10 H11 H12 H13 H14 H18 H20 H21 H22 H23 J1 J2 J3 J4 J6 J9 Default Signal VDDX RAD12 RAD14 RAD16 VDDX RAD23 SDBA1 VDDX SDA5 SDA0 VDDX VDDX RAD19 RAD20 VSS RAD26 SDQM3# SDBA0 SDA1 SDQM2# VDDX VDDX VDDI VDDI VDDI VDDX VDDX RAD25 RAD24 RAD28 RAD27 SDCKE SDCAS# SDQM0# SDQM1# SDCS2# VDDX Alternate Signal
AMD AlchemyTM AU1500TM Processor Data Book
243
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-1.
Pin No. J10 J11 J12 J13 J14 J15 J18 J20 J21 J22 J23 K1 K2 K3 K4 K6 K8 K9 K10 K11 K12 K13 K14 K15 K16 K18 K20 K21 K22 K23 L1 L2 L3 L4 L6 L8 L9 Default Signal VSS VSS VSS VSS VSS VDDX RBE2# RAD30 RAD29 RBE0# RAD31 SDWE# SDRAS# SDCLK2 SDCLK1 SDD31 VDDX VSS VSS VSS VSS VSS VSS VSS VDDI RCS2# RWE# RBE3# RBE1# ROE# SDCS0# SDCS1# SDD30 SDD27 SDD25 VDDI VSS
Pin Assignment -- Sorted by Pin Number (Continued)
Alternate Signal Pin No. L10 L11 L12 L13 L14 L15 L16 L18 L20 L21 L22 L23 M1 M2 M3 M4 M8 M9 M10 M11 M12 M13 M14 M15 M16 M20 M21 M22 M23 N1 N2 N3 N4 N6 N8 N9 N10 Default Signal VSS VSS VSS VSS VSS VSS VDDI PCI_STOP# U0RXD RCS1# RCS3# RCS0# SDD28 SDD29 SDD26 SDCLK0 VDDI VSS VSS VSS VSS VSS VSS VSS VDDI PCI_FRAME# PCI_IRDY# GPIO[23] GPIO[20] SDD24 SDD23 SDD22 SDD21 SDD17 VDDI VSS VSS U3TXD U0TXD Alternate Signal
244
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-1.
Pin No. N11 N12 N13 N14 N15 N16 N18 N20 N21 N22 N23 P1 P2 P3 P4 P6 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P20 P21 P22 P23 R1 R2 R3 R4 R6 R9 R10 Default Signal VSS VSS VSS VSS VSS VDDI PCI_REQ0# PCI_CLKO PCI_CLK PCI_DEVSEL# U3RXD SDD20 SDD19 SDD16 SDD15 SDD12 VDDX VSS VSS VSS VSS VSS VSS VDDX VDDX PCI_PAR PCI_GNT1# PCI_GNT0# PCI_LOCK# PCI_TRDY# SDD18 SDD14 SDD11 SDD8 VDDX VDDX VSS
Pin Assignment -- Sorted by Pin Number (Continued)
Alternate Signal Pin No. R11 R12 R13 R14 R15 R18 R20 R21 R22 R23 T1 T2 T3 T4 T6 T10 T11 T12 T13 T14 T18 T20 T21 T22 T23 U1 U2 U3 U4 U6 U18 U20 U21 U22 U23 V1 V2 Default Signal VSS VSS VSS VSS VDDX PCI_REQ3# PCI_SERR# PCI_CFG PCI_REQ2# PCI_REQ1# SDD13 VSS SDD9 SDD7 VDDX VDDX VDDI VDDI VDDI VDDI VDDX PCI_AD4 PCI_AD3 PCI_GNT3# PCI_GNT2# SDD10 VDDX SDD5 GPIO[15] VDDX VDDX PCI_AD10 PCI_AD8 VDDX PCI_PERR# SDD6 SDD4 Alternate Signal
AMD AlchemyTM AU1500TM Processor Data Book
245
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-1.
Pin No. V3 V4 V5 V7 V8 V9 V10 V11 V13 V14 V15 V16 V17 V19 V20 V21 V22 V23 W1 W2 W3 W4 W5 W6 W18 W19 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
246
Pin Assignment -- Sorted by Pin Number (Continued)
Alternate Signal U3DTR# Pin No. Y10 Y11 Y12 Y13 Y14 N1TXD2 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 DMA_REQ2 AA10 AA11 AA12 AA13 AA14 AA15 AA16 U3RTS# AA17 AA18 AA19 AA20 AA21 AA22 AA23 N1TXD3 N1TXD0 AB1 AB2 Default Signal N0MDIO N0TXD3 N0RXDV N0RXCLK GPIO[202] PCI_INTC# PCI_INTA# PCI_AD25 PCI_AD21 USBDP USBDM PCI_AD13 PCI_AD9 PCI_AD7 ACSYNC ACBCLK GPIO[8] GPIO[209] TDI GPIO[207] GPIO[206] TCK GPIO[26] N1RXD1 N0TXD1 N0TXEN GPIO[203] GPIO[201] PCI_CBE3# PCI_CBE1# PCI_AD31 PCI_AD26 PCI_AD22 PCI_AD20 USBH1P VDDX PCI_AD12 ACDI VSS
AMD AlchemyTM AU1500TM Processor Data Book
Default Signal GPIO[14] SDD0 SDD1 VDDX VDDX GPIO[27] N1CRS N0COL N0RXD3 N0RXD2 PCI_INTB# VDDX VDDX PCI_AD11 PCI_AD15 PCI_AD6 VSS PCI_AD0 SDD3 SDD2 ACRST# GPIO[214] GPIO[211] GPIO[208] PCI_AD16 PCI_AD17 USBH1M PCI_AD5 PCI_AD2 PCI_AD1 GPIO[13] ACDO GPIO[11] GPIO[215] GPIO[12] GPIO[212] GPIO[210] GPIO[28] GPIO[25]
Alternate Signal
USBH0P USBH0M
DMA_REQ3
N1TXD1
U3DCD#
U3RI#
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-1.
Pin No. AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 Default Signal VDDX TDO N1COL VSS VDDX N1RXD3 GPIO[24] N1RXD0 N1TXCLK GPIO[205] N0RXD1 N0CRS PCI_RST# PCI_INTD# VSS VDDX PCI_AD29 PCI_AD27 PCI_AD23 VSS PCI_AD14 GPIO[10]
Pin Assignment -- Sorted by Pin Number (Continued)
Alternate Signal Pin No. AC2 AC3 AC4 AC5 AC6 AC7 N1TXEN AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 U3DSR# Default Signal GPIO[9] GPIO[213] N1MDIO N1MDC N1RXDV N1RXCLK N1RXD2 N0MDC N0TXD2 N0TXD0 GPIO[204] N0RXD0 N0TXCLK GPIO[200] PCI_CBE2# PCI_CBE0# PCI_IDSEL PCI_AD30 PCI_AD28 PCI_AD24 PCI_AD19 PCI_AD18 PCI_RSTO# Alternate Signal U3CTS#
AMD AlchemyTM AU1500TM Processor Data Book
247
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-2. Pin Assignment -- Sorted Alphabetically by Default Signal
Default Signal ACBCLK ACDI ACDO ACRST# ACSYNC EWAIT# GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[20] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[200] GPIO[201] GPIO[202] GPIO[203] GPIO[204] GPIO[205] GPIO[206] GPIO[207] GPIO[208] GPIO[209] DMA_REQ2 DMA_REQ3 U0TXD U3TXD N1TXEN N1TXD0 N1TXD1 N1TXD2 N1TXD3 PCI_RSTO# U3CTS# U3DSR# U3DCD# U3RI# U3RTS# U3DTR# EXTCLK0 EXTCLK1 DMA_REQ0 DMA_REQ1 SMROMCKE Alternate Signal Pin No. AA2 AB1 Y2 W3 AA1 A12 E6 D6 A7 D7 A8 B8 D9 D10 AA3 AC2 AC1 Y3 Y5 Y1 V3 U4 M23 M22 AB9 Y9 AA9 V9 Y8 AC15 AA14 Y14 AA13 AC12 AB12 AA7 AA6 W6 AA4 Default Signal GPIO[210] GPIO[211] GPIO[212] GPIO[213] GPIO[214] GPIO[215] LCLK LRD0# LRD1# LWAIT# LWR0# LWR1# N0COL N0CRS N0MDC N0MDIO N0RXCLK N0RXD0 N0RXD1 N0RXD2 N0RXD3 N0RXDV N0TXCLK N0TXD0 N0TXD1 N0TXD2 N0TXD3 N0TXEN N1COL N1CRS N1MDC N1MDIO N1RXCLK N1RXD0 N1RXD1 N1RXD2 N1RXD3 N1RXDV N1TXCLK Alternate Signal Pin No. Y7 W5 Y6 AC3 W4 Y4 D12 C11 D11 B11 F11 C12 V11 AB14 AC9 Y10 Y13 AC13 AB13 V14 V13 Y12 AC14 AC11 AA11 AC10 Y11 AA12 AB5 V10 AC5 AC4 AC7 AB10 AA10 AC8 AB8 AC6 AB11
248
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-2.
Default Signal PCE1# PCE2# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_CFG
Pin Assignment -- Sorted Alphabetically by Default Signal (Continued)
Pin No. B10 A11 V23 W23 W22 T21 T20 W21 V21 Y23 U21 Y22 U20 V19 AA23 Y21 AB23 V20 W18 W19 AC23 AC22 AA20 Y18 AA19 AB21 AC21 Y17 AA18 AB20 AC20 AB19 AC19 AA17 AC17 AA16 AC16 AA15 R21 Default Signal PCI_CLK PCI_CLKO PCI_DEVSEL# PCI_FRAME# PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_IDSEL PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_IRDY# PCI_LOCK# PCI_PAR PCI_PERR# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# PIOR# PIOS16# PIOW# POE# PREG# PWAIT# PWE# PWR_EN RAD0 RAD1 RAD2 RAD3 RAD4 RAD5 Alternate Signal Pin No. N21 N20 N22 M20 P21 P20 T23 T22 AC18 Y16 V15 Y15 AB16 M21 P22 P18 U23 N18 R23 R22 R18 AB15 R20 L18 P23 A9 F9 C9 B9 A10 F10 C10 E5 C20 A21 C21 C22 B23 A22
Alternate Signal
AMD AlchemyTM AU1500TM Processor Data Book
249
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-2.
Default Signal RAD6 RAD7 RAD8 RAD9 RAD10 RAD11 RAD12 RAD13 RAD14 RAD15 RAD16 RAD17 RAD18 RAD19 RAD20 RAD21 RAD22 RAD23 RAD24 RAD25 RAD26 RAD27 RAD28 RAD29 RAD30 RAD31 RBE0# RBE1# RBE2# RBE3# RCS0# RCS1# RCS2# RCS3# RD0 RD1 RD2 RD3 RD4
Pin Assignment -- Sorted Alphabetically by Default Signal (Continued)
Pin No. D20 D19 A23 E20 E19 E21 F19 C23 F20 D21 F21 D22 D23 G20 G21 E22 E23 F23 H21 H20 G23 H23 H22 J21 J20 J23 J22 K22 J18 K21 L23 L21 K18 L22 F13 B12 A13 B13 C13 Default Signal RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RD16 RD17 RD18 RD19 RD20 RD21 RD22 RD23 RD24 RD25 RD26 RD27 RD28 RD29 RD30 RD31 RESETIN# RESETOUT# ROE# ROMSEL ROMSIZE RWE# SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 Alternate Signal Pin No. D13 A14 B14 A15 F14 D14 C14 B15 F15 B16 C15 D15 A16 A17 A18 D16 C16 D17 A19 A20 B19 C17 C18 C19 E18 B20 D18 A6 D3 K23 C5 D5 K20 G4 H3 F1 E1 E2 G3
Alternate Signal
250
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-2.
Default Signal SDA6 SDA7 SDA8 SDA9 SDA10 SDA11 SDA12 SDBA0 SDBA1 SDCAS# SDCKE SDCLK0 SDCLK1 SDCLK2 SDCS0# SDCS1# SDCS2# SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD16 SDD17 SDD18 SDD19 SDD20 SDD21
Pin Assignment -- Sorted Alphabetically by Default Signal (Continued)
Pin No. F5 D1 C1 F3 F4 E3 E4 H2 G1 J2 J1 M4 K4 K3 L1 L2 J6 V4 V5 W2 W1 V2 U3 V1 T4 R4 T3 U1 R3 P6 T1 R2 P4 P3 N6 R1 P2 P1 N4 Default Signal SDD22 SDD23 SDD24 SDD25 SDD26 SDD27 SDD28 SDD29 SDD30 SDD31 SDQM0# SDQM1# SDQM2# SDQM3# SDRAS# SDWE# TC0 TC1 TC2 TC3 TCK TDI TDO TESTEN TMS TRST# U0RXD U3RXD USBDM USBDP USBH1M USBH1P VDDI USBH0M USBH0P Alternate Signal Pin No. N3 N2 N1 L6 M3 L4 M1 M2 L3 K6 J3 J4 H4 H1 K2 K1 C6 C7 C8 D8 AA8 AA5 AB4 B1 C3 D4 L20 N23 Y20 Y19 W20 AA21 H11, H12, H13, K16, L8, L16, M8, M16, N8, N16, T11, T12, T13, T14
Alternate Signal
AMD AlchemyTM AU1500TM Processor Data Book
251
www..com
30361D Packaging, Pin Assignments, and Ordering Information
Table 13-2.
Default Signal VDDX
Pin Assignment -- Sorted Alphabetically by Default Signal (Continued)
Pin No. B6, B17, B21, D2, F7, F8, F16, F17, F22, G2, G6, G18, H6, H10, H14, H18, J9, J15, K8, P8, P15, P16, R6, R9, R15, T6, T10, T18, U2, U6, U18, U22, V7, V8, V16, V17, AA22, AB3, AB7, AB18 C4 B7, B18, B22, C2, F2, G22, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, K15, L9, L10, L11, L12, L13, L14, L15, M9, M10, M11, M12, M13, M14, M15, N9, N10, N11, N12, N13, N14, N15, P9, P10, P11, P12, P13, P14, R10, R11, R12, R13, R14, T2, V22, AB2, AB6, AB17, AB22 Default Signal XAGND12 XAGND32 XPWR12 XPWR32 XTI12 XTI32 XTO12 XTO32 Alternate Signal Pin No. B5 B3 B4 B2 A5 A3 A4 A2
Alternate Signal
VDDXOK VSS
252
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Packaging, Pin Assignments, and Ordering Information 30361D
Table 13-3. Pin Assignment -- Alternate Signals Sorted Alphabetically
Alternate Signal EXTCLK0 EXTCLK1 DMA_REQ0 DMA_REQ1 DMA_REQ2 DMA_REQ3 N1TXD0 N1TXD1 N1TXD2 N1TXD3 N1TXEN PCI_RSTO# SMROMCKE U0TXD U3CTS# U3DCD# U3DSR# U3DTR# U3RI# U3RTS# U3TXD USBH0M USBH0P Default Signal GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[208] GPIO[209] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[24] GPIO[200] GPIO[6] GPIO[20] GPIO[9] GPIO[11] GPIO[10] GPIO[14] GPIO[12] GPIO[13] GPIO[23] USBDM USBDP Pin No. A7 D7 A8 B8 AA3 AA4 Y9 AA9 V9 Y8 AB9 AC15 D9 M23 AC2 Y3 AC1 V3 Y5 Y1 M22 Y20 Y19
AMD AlchemyTM AU1500TM Processor Data Book
253
www..com
30361D Packaging, Pin Assignments, and Ordering Information
13.3
Ordering Information
Ordering information for the AMD AlchemyTM AU1500TM processor is contained in this section. The ordering part number (OPN) is formed by a combination of elements. An example of the OPN is shown in Figure 13-3. Valid OPN combinations are provided in Table 13-4.
OPN (Note) AU1500 333 MB C Temperature Range C = Commercial (TCASE = 0C to +85C) D = Commercial Pb-Free (TCASE = 0C to +85C) I = Industrial (TCASE = -40C to +100C) F = Industrial Pb-Free (TCASE = -40C to +100C) Package Type MB = Low profile PBGA package (0.8 mm ball-pitch) Speed Option 333 = 333 MHz 400 = 400 MHz 500 = 500 MHz Device Number Note: Spaces are added to the ordering number shown above for viewing clarity only.
Figure 13-3. OPN Example
Table 13-4. Valid OPN Combinations
Device Number AU1500 Speed Option 333 Package Type MB Temperature Range C D I F AU1500 400 MB C D AU1500 500 MB C D Note: Consult your local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations possibly not listed.
254
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
Appendix ASupport Documentation
A.1 Memory Map
A
The peripheral devices on the AU1500 processor contain memory-mapped registers visible to software. Table A-1 contains the memory map for the peripheral devices and physical memory. The addresses are 36 bits wide.
Table A-1. Basic AU1500TM Processor Physical Address Memory Map
Start Address 0x0 0000 0000 0x0 1000 0000 0x0 1200 0000 0x0 1400 0000 0x0 1800 0000 0x0 2000 0000 0x0 8000 0000 0x0 F000 0000 0x1 0000 0000 0x4 0000 0000 0x5 0000 0000 0x6 0000 0000 0x7 0000 0000 0xD 0000 0000 0xE 0000 0000 0xF 0000 0000 End Address 0x0 0FFF FFFF 0x0 11FF FFFF 0x0 13FF FFFF 0x0 17FF FFFF 0x0 1FFF FFFF 0x0 7FFF FFFF 0x0 EFFF FFFF 0x0 FFFF FFFF 0x3 FFFF FFFF 0x4 FFFF FFFF 0x5 FFFF FFFF 0x6 FFFF FFFF 0xC FFFF FFFF 0xD FFFF FFFF 0xE FFFF FFFF 0xF FFFF FFFF Size (MB) 256 32 32 64 128 1536 1792 256 4096 * 3 4096 4096 4096 4096 * 7 4096 4096 4096 Function Memory KSEG 0/1 I/O Devices on Peripheral Bus Reserved I/O Devices on System Bus Memory Mapped. 0x0 1FC0 0000 must contain the boot vector so this is typically where Flash or ROM is located. Memory Mapped Memory Mapped. Currently this space is memory mapped, but it should be considered reserved for future use. Debug Probe Reserved PCI Uncached Memory Space PCI I/O Space PCI Configuration Space Reserved I/O Device External LCD Controller Interface PCMCIA Interface
The AU1500 processor system bus devices are mapped at the addresses based at 0x0 1400 0000. See Table A-2 for complete addresses.
Table A-2. System Bus Devices Physical Address Memory Map
Start Address 0x0 1400 0000 0x0 1400 1000 0x0 1400 2000 0x0 1400 4000 End Address 0x0 1400 0FFF 0x0 1400 1FFF 0x0 1400 2FFF 0x0 1400 4FFF Size 4 KB 4 KB 4 KB 4 KB Function SDRAM Memory Controller SRAM/Flash Memory Controller DMA Ethernet DMA
AMD AlchemyTM AU1500TM Processor Data Book
255
www..com
30361D Support Documentation
The AU1500 processor peripheral bus devices are based at 0x0 1100 0000. The individual memory spaces of the devices are defined in Table A-3.
Table A-3. Peripheral Bus Devices Physical Address Memory Map
Start Address 0x0 1000 0000 0x0 1010 0000 0x0 1020 0000 0x0 1030 0000 0x0 1040 0000 0x0 1050 0000 0x0 1110 0000 0x0 1120 0000 0x0 1140 0000 0x0 1150 0000 0x0 1160 0000 0x0 1170 0000 0x0 1180 0000 0x0 1190 0000 End Address 0x0 100F FFFF 0x0 101F FFFF 0x0 102F FFFF 0x0 103F FFFF 0x0 104F FFFF 0x0 110F FFFF 0x0 111F FFFF 0x0 113F FFFF 0x0 114F FFFF 0x0 115F FFFF 0x0 116F FFFF 0x0 117F FFFF 0x0 118F FFFF 0x0 119F FFFF Size 1 MB 1 MB 1 MB 1 MB 1 MB 12 MB 1 MB 2 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB Secondary GPIO Interrupt Controller 1 System Control: RTC, TOY, Timers, Primary GPIO, Power Management UART3 Ethernet MAC UART0 Interrupt Controller 0 Function AC97 Controller USB Host USB Device
256
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
A.1.1
Device Memory Map
Table A-4 lists all of the devices which are memory mapped to the AU1500 processor core. These devices are all mapped within KSEG1 (non-cached, non-TLB). All 32-bit addresses are translated into 36-bit addresses by changing bits [31:29] to zero and adding bits [35:32] which are set to zero.
Table A-4. Device Memory Map
Register KSEG1 Address Physical Address Register ic0_cfg1set 0x0 1000 0000 0x0 1000 0004 0x0 1000 0008 0x0 100 0000C 0x0 1000 000C 0x0 1000 0010 ic0_cfg1clr ic0_cfg2rd ic0_cfg2set ic0_cfg2clr ic0_req0int ic0_srcrd ic0_srcset ic0_srcclr Open HCI Register Set Base usbh_enable 0xB010 0000 0xB017 FFFC 0x0 1010 0000 0x0 1017 FFFC ic0_req1int ic0_assignrd ic0_assignset ic0_assignclr ic0_wakerd ic0_wakeset ic0_wakeclr ic0_maskrd ic0_maskset ic0_maskclr ic0_risingrd ic0_risingclr ic0_fallingrd ic0_fallingclr KSEG1 Address 0xB040 0048 0xB040 004C 0xB040 0050 0xB040 0050 0xB040 0054 0xB040 0054 0xB040 0058 0xB040 0058 0xB040 005C 0xB040 005C 0xB040 0060 0xB040 0060 0xB040 0064 0xB040 0068 0xB040 006C 0xB040 0070 0xB040 0070 0xB040 0074 0xB040 0078 0xB040 0078 0xB040 007C 0xB040 007C 0xB040 0080 Physical Address 0x0 1040 0048 0x0 1040 004C 0x0 1040 0050 0x0 1040 0050 0x0 1040 0054 0x0 1040 0054 0x0 1040 0058 0x0 1040 0058 0x0 1040 005C 0x0 1040 005C 0x0 1040 0060 0x0 1040 0060 0x0 1040 0064 0x0 1040 0068 0x0 1040 006C 0x0 1040 0070 0x0 1040 0070 0x0 1040 0074 0x0 1040 0078 0x0 1040 0078 0x0 1040 007C 0x0 1040 007C 0x0 1040 0080
AC97 Controller- Section 7.1 on page 102 ac97_config ac97_status ac97_data ac97_cmmd ac97_cmmdresp ac97_control 0xB000 0000 0xB000 0004 0xB000 0008 0xB000 000C 0xB000 000C 0xB000 0010
USB Host Controller - Section 7.2 on page 107
USB Device Controller - Section 7.3 on page 109 usbd_ep0rd usbd_ep0wr usbd_ep1wr usbd_ep2wr usbd_ep3rd usbd_ep4rd usbd_inten usbd_intstat usbd_config usbd_ep0cs usbd_ep1cs usbd_ep2cs usbd_ep3cs usbd_ep4cs usbd_ep0rdstat usbd_ep0wrstat usbd_ep1wrstat usbd_ep2wrstat usbd_ep3rdstat usbd_ep4rdstat usbd_enable 0xB020 0000 0xB020 0004 0xB020 0008 0xB020 000C 0xB020 0010 0xB020 0014 0xB020 0018 0xB020 001C 0xB020 0020 0xB020 0024 0xB020 0028 0xB020 002C 0xB020 0030 0xB020 0034 0xB020 0040 0xB020 0044 0xB020 0048 0xB020 004c 0xB020 0050 0xB020 0054 0xB020 0058 0x0 1020 0000 0x0 1020 0004 0x0 1020 0008 0x0 1020 000C 0x0 1020 0010 0x0 1020 0014 0x0 1020 0018 0x0 1020 001c 0x0 1020 0020 0x0 1020 0024 0x0 1020 0028 0x0 1020 002C 0x0 1020 0030 0x0 1020 0034 0x0 1020 0040 0x0 1020 0044 0x0 1020 0048 0x0 1020 004c 0x0 1020 0050 0x0 1020 0054 0x0 1020 0058
UART0 - Section 7.5.2 on page 140 uart0_rxdata uart0_txdata uart0_inten uart0_intcause uart0_fifoctrl uart0_linectrl -- uart0_linestat -- uart0_clkdiv uart0_enable 0xB110 0000 0xB110 0004 0xB110 0008 0xB110 000C 0xB110 0010 0xB110 0014 0xB110 0018 0xB110 001C 0xB110 0020 0xB110 0028 0xB110 0100 0x0 1110 0000 0x0 1110 0004 0x0 1110 0008 0x0 1110 000C 0x0 1110 0010 0x0 1110 0014 0x0 1110 0018 0x0 1110 001C 0x0 1110 0020 0x0 1110 0028 0x0 1110 0100
Interrupt Controller 0 - Section 6.2 on page 97 ic0_cfg0rd ic0_cfg0set ic0_cfg0clr ic0_cfg1rd 0xB040 0040 0xB040 0040 0xB040 0044 0xB040 0048 0x0 1040 0040 0x0 1040 0040 0x0 1040 0044 0x0 1040 0048
UART3 - Section 7.5.2 on page 140 uart3_rxdata uart3_txdata 0xB140 0000 0xB140 0004 0x0 1140 0000 0x0 1140 0004 257
AMD AlchemyTM AU1500TM Processor Data Book
www..com
30361D Support Documentation
Table A-4.
Register uart3_inten uart3_intcause uart3_fifoctrl uart3_linectrl uart3_mdmctrl uart3_linestat uart3_mdmstat uart3_autoflow uart3_clkdiv uart3_enable KSEG1 Address 0xB140 0008 0xB140 000C 0xB140 0010 0xB140 0014 0xB140 0018 0xB140 001C 0xB140 0020 0xB140 0024 0xB140 0028 0xB140 0100
Device Memory Map (Continued)
Register gpio2_enable KSEG1 Address 0xB170 0014 Physical Address 0x0 1170 0014
Physical Address 0x0 1140 0008 0x0 1140 000C 0x0 1140 0010 0x0 1140 0014 0x0 1140 0018 0x0 1140 001C 0x0 1140 0020 0x0 1140 0024 0x0 1140 0028 0x0 1140 0100
Interrupt Controller 1 - Section 6.2 on page 97 ic1_cfg0rd ic1_cfg0set ic1_cfg0clr ic1_cfg1rd ic1_cfg1set ic1_cfg1clr ic1_cfg2rd ic1_cfg2set ic1_cfg2clr ic1_req0int ic1_srcrd ic1_srcset ic1_srcclr ic1_req1int ic1_assignrd ic1_assignset ic1_assignclr ic1_wakerd ic1_wakeset ic1_wakeclr ic1_maskrd ic1_maskset ic1_maskclr ic1_risingrd ic1_risingclr ic1_fallingrd ic1_fallingclr 0xB180 0040 0xB180 0040 0xB180 0044 0xB180 0048 0xB180 0048 0xB180 004C 0xB180 0050 0xB180 0050 0xB180 0054 0xB180 0054 0xB180 0058 0xB180 0058 0xB180 005C 0xB180 005C 0xB180 0060 0xB180 0060 0xB180 0064 0xB180 0068 0xB180 006C 0xB180 0070 0xB180 0070 0xB180 0074 0xB180 0078 0xB180 0078 0xB180 007C 0xB180 007C 0xB180 0080 0x0 1180 0040 0x0 1180 0040 0x0 1180 0044 0x0 1180 0048 0x0 1180 0048 0x0 1180 004C 0x0 1180 0050 0x0 1180 0050 0x0 1180 0054 0x0 1180 0054 0x0 1180 0058 0x0 1180 0058 0x0 1180 005C 0x0 1180 005C 0x0 1180 0060 0x0 1180 0060 0x0 1180 0064 0x0 1180 0068 0x0 1180 006C 0x0 1180 0070 0x0 1180 0070 0x0 1180 0074 0x0 1180 0078 0x0 1180 0078 0x0 1180 007C 0x0 1180 007C 0x0 1180 0080
Ethernet Controller MAC0 - Section 7.4.2 on page 120 mac0_control mac0_addrhigh mac0_addrlow mac0_hashhigh mac0_hashlow mac0_miictrl mac0_miidata mac0_flowctrl mac0_vlan1 mac0_vlan2 0xB150 0000 0xB150 0004 0xB150 0008 0xB150 000C 0xB150 0010 0xB150 0014 0xB150 0018 0xB150 001C 0xB150 0020 0xB150 0024 0x0 1150 0000 0x0 1150 0004 0x0 1150 0008 0x0 1150 000C 0x0 1150 0010 0x0 1150 0014 0x0 1150 0018 0x0 1150 001C 0x0 1150 0020 0x0 1150 0024
Ethernet Controller MAC1 - Section 7.4.2 on page 120 mac1_control mac1_addrhigh mac1_addrlow mac1_hashhigh mac1_hashlow mac1_miictrl mac1_miidata mac1_flowctrl mac1_vlan1 mac1_vlan2 0xB151 0000 0xB151 0004 0xB151 0008 0xB151 000C 0xB151 0010 0xB151 0014 0xB151 0018 0xB151 001C 0xB151 0020 0xB151 0024 0x0 1151 0000 0x0 1151 0004 0x0 1151 0008 0x0 1151 000C 0x0 1151 0010 0x0 1151 0014 0x0 1151 0018 0x0 1151 001C 0x0 1151 0020 0x0 1151 0024
Clock Controller - Section 8.1.1 on page 155 sys_freqctrl0 sys_freqctrl1 sys_clksrc sys_cpupll sys_auxpll 0xB190 0020 0xB190 0024 0xB190 0028 0xB190 0060 0xB190 0064 0x0 1190 0020 0x0 1190 0024 0x0 1190 0028 0x0 1190 0060 0x0 1190 0064
Ethernet Controller Enable - Section 7.4.3 on page 128 macen_mac0 macen_mac1 0xB152 0000 0xB152 0004 0x0 1152 0000 0x0 1152 0004
Secondary GPIO - Section 7.6.2 on page 149 gpio2_dir reserved gpio2_output gpio2_pinstate gpio2_inten 258 0xB170 0000 0xB170 0004 0xB170 0008 0xB170 000C 0xB170 0010 0x0 1170 0000 0x0 1170 0004 0x0 1170 0008 0x0 1170 000C 0x0 1170 0010
TOY & RTC - Section 8.2.1 on page 164 sys_toytrim sys_toywrite sys_matchtoy0 sys_matchtoy1 sys_matchtoy2 0xB190 0000 0xB190 0004 0xB190 0008 0xB190 000C 0xB190 0010 0x0 1190 0000 0x0 1190 0004 0x0 1190 0008 0x0 1190 000C 0x0 1190 0010
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
Table A-4.
Register sys_cntrctrl sys_toyread sys_rtctrim sys_rtcwrite sys_rtcmatch0 sys_rtcmatch1 sys_rtcmatch2 sys_rtcread KSEG1 Address 0xB190 0014 0xB190 0040 0xB190 0044 0xB190 0048 0xB190 004C 0xB190 0050 0xB190 0054 0xB190 0058
Device Memory Map (Continued)
Register KSEG1 Address Physical Address
Physical Address 0x0 1190 0014 0x0 1190 0040 0x0 1190 0044 0x0 1190 0048 0x0 1190 004C 0x0 1190 0050 0x0 1190 0054 0x0 1190 0058
Static Bus Controller - Section 3.2.1 on page 53 mem_stcfg0 mem_sttime0 mem_staddr0 mem_stcfg1 mem_sttime1 mem_staddr1 mem_stcfg2 mem_sttime2 0xB190 1000 0xB190 1004 0xB190 1008 0xB190 1010 0xB190 1014 0xB190 1018 0xB190 1020 0xB190 1024 0xB190 1028 0xB190 1030 0xB190 1034 0xB190 1038 0x0 1400 1000 0x0 1400 1004 0x0 1400 1008 0x0 1400 1010 0x0 1400 1014 0x0 1400 1018 0x0 1400 1020 0x0 1400 1024 0x0 1400 1028 0x0 1400 1030 0x0 1400 1034 0x0 1400 1038
Primary GPIO - Section 8.3.2 on page 169 sys_pinfunc sys_trioutrd sys_trioutclr sys_outputrd sys_outputset sys_outputclr sys_pinstaterd sys_pininputen 0xB190 002C 0xB190 0100 0xB190 0100 0xB190 0108 0xB190 0108 0xB190 010C 0xB190 0110 0xB190 0110 0x0 1190 002C 0x0 1190 0100 0x0 1190 0100 0x0 1190 0108 0x0 1190 0108 0x0 1190 010C 0x0 1190 0110 0x0 1190 0110
mem_staddr2 mem_stcfg3 mem_sttime3 mem_staddr3
DMA Controller 0 - Section 5.1 on page 87 dma0_moderead dma0_modeset dma0_modeclr dma0_peraddr dma0_buf0addr dma0_buf0size dma0_buf1addr dma0_buf1size 0xB190 2000 0xB190 2000 0xB190 2004 0xB190 2008 0xB190 200C 0xB190 2010 0xB190 2014 0xB190 2018 0x0 1400 2000 0x0 1400 2000 0x0 1400 2004 0x0 1400 2008 0x0 1400 200C 0x0 1400 2010 0x0 1400 2014 0x0 1400 2018
Power Management - Section 8.4.5 on page 175 sys_scratch0 sys_scratch1 sys_wakemsk sys_endian sys_powerctrl sys_wakesrc sys_slppwr sys_sleep 0xB190 0018 0xB190 001C 0xB190 0034 0xB190 0038 0xB190 003C 0xB190 005C 0xB190 0078 0xB190 007C 0x0 1190 0018 0x0 1190 001C 0x0 1190 0034 0x0 1190 0038 0x0 1190 003C 0x0 1190 005C 0x0 1190 0078 0x0 1190 007C
DMA Controller 1 - Section 5.1 on page 87 dma1_moderead dma1_modeset dma1_modeclr dma1_peraddr dma1_buf0addr dma1_buf0size dma1_buf1addr dma1_buf1size 0xB190 2100 0xB190 2100 0xB190 2104 0xB190 2108 0xB190 210C 0xB190 2110 0xB190 2114 0xB190 2118 0x0 1400 2100 0x0 1400 2100 0x0 1400 2104 0x0 1400 2108 0x0 1400 210C 0x0 1400 2110 0x0 1400 2114 0x0 1400 2118
SDRAM Controller - Section 3.1.2 on page 45 mem_sdmode0 mem_sdmode1 mem_sdmode2 mem_sdaddr0 mem_sdaddr1 mem_sdaddr2 mem_sdrefcfg mem_sdprecmd mem_sdautoref mem_sdwrmd0 mem_sdwrmd1 mem_sdwrmd2 mem_sdsleep mem_sdsmcke 0xB190 0000 0xB190 0004 0xB190 0008 0xB190 000C 0xB190 0010 0xB190 0014 0xB190 0018 0xB190 001C 0xB190 0020 0xB190 0024 0xB190 0028 0xB190 002C 0xB190 0030 0xB190 0034 0x0 1400 0000 0x0 1400 0004 0x0 1400 0008 0x0 1400 000C 0x0 1400 0010 0x0 1400 0014 0x0 1400 0018 0x0 1400 001C 0x0 1400 0020 0x0 1400 0024 0x0 1400 0028 0x0 1400 002C 0x0 1400 0030 0x0 1400 0034
DMA Controller 2 - Section 5.1 on page 87 dma2_moderead dma2_modeset dma2_modeclr dma2_peraddr dma2_buf0addr dma2_buf0size dma2_buf1addr dma2_buf1size 0xB190 2200 0xB190 2200 0xB190 2204 0xB190 2208 0xB190 220C 0xB190 2210 0xB190 2214 0xB190 2218 0x0 1400 2200 0x0 1400 2200 0x0 1400 2204 0x0 1400 2208 0x0 1400 220C 0x0 1400 2210 0x0 1400 2214 0x0 1400 2218
AMD AlchemyTM AU1500TM Processor Data Book
259
www..com
30361D Support Documentation
Table A-4.
Register KSEG1 Address
Device Memory Map (Continued)
Register dma7_peraddr KSEG1 Address 0xB190 2708 0xB190 270C 0xB190 2710 0xB190 2714 0xB190 2718 Physical Address 0x0 1400 2708 0x0 1400 270C 0x0 1400 2710 0x0 1400 2714 0x0 1400 2718
Physical Address
DMA Controller 3 - Section 5.1 on page 87 dma3_moderead dma3_modeset dma3_modeclr dma3_peraddr dma3_buf0addr dma3_buf0size dma3_buf1addr dma3_buf1size 0xB190 2300 0xB190 2300 0xB190 2304 0xB190 2308 0xB190 230C 0xB190 2310 0xB190 2314 0xB190 2318 0x0 1400 2300 0x0 1400 2300 0x0 1400 2304 0x0 1400 2308 0x0 1400 230C 0x0 1400 2310 0x0 1400 2314 0x0 1400 2318
dma7_buf0addr dma7_buf0size dma7_buf1addr dma7_buf1size
Ethernet Controller DMA Channels -Section 7.4.4 on page 129 macdma0_tx0stat macdma0_tx0addr macdma0_tx0len macdma0_tx1stat 0xB190 4000 0xB190 4004 0xB190 4008 0xB190 4010 0xB190 4014 0xB190 4018 0xB190 4020 0xB190 4024 0xB190 4028 0xB190 4030 0xB190 4034 0xB190 4038 0xB190 4100 0xB190 4104 0xB190 4110 0xB190 4114 0xB190 4120 0xB190 4124 0xB190 4130 0xB190 4134 0xB190 4200 0xB190 4204 0xB190 4208 0xB190 4210 0xB190 4214 0xB190 4218 0xB190 4220 0xB190 4224 0xB190 4228 0xB190 4230 0xB190 4234 0xB190 4238 0xB190 4300 0xB190 4304 0xB190 4310 0x0 1400 4000 0x0 1400 4004 0x0 1400 4008 0x0 1400 4010 0x0 1400 4014 0x0 1400 4018 0x0 1400 4020 0x0 1400 4024 0x0 1400 4028 0x0 1400 4030 0x0 1400 4034 0x0 1400 4038 0x0 1400 4100 0x0 1400 4104 0x0 1400 4110 0x0 1400 4114 0x0 1400 4120 0x0 1400 4124 0x0 1400 4130 0x0 1400 4134 0x0 1400 4200 0x0 1400 4204 0x0 1400 4208 0x0 1400 4210 0x0 1400 4214 0x0 1400 4218 0x0 1400 4220 0x0 1400 4224 0x0 1400 4228 0x0 1400 4230 0x0 1400 4234 0x0 1400 4238 0x0 1400 4300 0x0 1400 4304 0x0 1400 4310
DMA Controller 4- Section 5.1 on page 87 dma4_moderead dma4_modeset dma4_modeclr dma4_peraddr dma4_buf0addr dma4_buf0size dma4_buf1addr dma4_buf1size 0xB190 2400 0xB190 2400 0xB190 2404 0xB190 2408 0xB190 240C 0xB190 2410 0xB190 2414 0xB190 2418 0x0 1400 2400 0x0 1400 2400 0x0 1400 2404 0x0 1400 2408 0x0 1400 240C 0x0 1400 2410 0x0 1400 2414 0x0 1400 2418
macdma0_tx1addr macdma0_tx1len macdma0_tx2stat macdma0_tx2addr macdma0_tx2len macdma0_tx3stat macdma0_tx3addr macdma0_tx3len macdma0_rx0stat macdma0_rx0addr
DMA Controller 5 - Section 5.1 on page 87 dma5_moderead dma5_modeset dma5_modeclr dma5_peraddr dma5_buf0addr dma5_buf0size dma5_buf1addr dma5_buf1size 0xB190 2500 0xB190 2500 0xB190 2504 0xB190 2508 0xB190 250C 0xB190 2510 0xB190 2514 0xB190 2518 0x0 1400 2500 0x0 1400 2500 0x0 1400 2504 0x0 1400 2508 0x0 1400 250C 0x0 1400 2510 0x0 1400 2514 0x0 1400 2518
macdma0_rx1stat macdma0_rx1addr macdma0_rx2stat macdma0_rx2addr macdma0_rx3stat macdma0_rx3addr macdma1_tx0stat macdma1_tx0addr macdma1_tx0len
DMA Controller 6 - Section 5.1 on page 87 dma6_moderead dma6_modeset dma6_modeclr dma6_peraddr dma6_buf0addr dma6_buf0size dma6_buf1addr dma6_buf1size 0xB190 2600 0xB190 2600 0xB190 2604 0xB190 2608 0xB190 260C 0xB190 2610 0xB190 2614 0xB190 2618 0x0 1400 2600 0x0 1400 2600 0x0 1400 2604 0x0 1400 2608 0x0 1400 260C 0x0 1400 2610 0x0 1400 2614 0x0 1400 2618
macdma1_tx1stat macdma1_tx1addr macdma1_tx1len macdma1_tx2stat macdma1_tx2addr macdma1_tx2len macdma1_tx3stat macdma1_tx3addr macdma1_tx3len
DMA Controller 7 - Section 5.1 on page 87 dma7_moderead dma7_modeset dma7_modeclr 0xB190 2700 0xB190 2700 0xB190 2704 0x0 1400 2700 0x0 1400 2700 0x0 1400 2704
macdma1_rx0stat macdma1_rx0addr macdma1_rx1stat
260
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
Table A-4.
Register
Device Memory Map (Continued)
KSEG1 Address 0xB190 4314 0xB190 4320 0xB190 4324 0xB190 4330 0xB190 4334 Physical Address 0x0 1400 4314 0x0 1400 4320 0x0 1400 4324 0x0 1400 4330 0x0 1400 4334
A.1.2
Programming Tips
macdma1_rx1addr macdma1_rx2stat macdma1_rx2addr macdma1_rx3stat macdma1_rx3addr
A.1.2.1 Memory Mapped Registers Peripheral, or system device registers should all be marked with the CCA bits to non-cacheable. Access must be on 32-bit boundaries, one 32-bit value at a time. See Section 2.2 "Caches" on page 17 for more information.
AMD AlchemyTM AU1500TM Processor Data Book
261
www..com
30361D Support Documentation
A.2
Data Book Notations
This section addresses some of the terminology used in this book.
A.2.1
Unpredictable and Undefined
The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations. A.2.1.1 Unpredictable UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is generated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions. UNPREDICTABLE results or operations have several implementation restrictions: * Implementations of operations generating UNPREDICTABLE results must not depend on any data source (memory or internal state) which is inaccessible in the current processor mode * UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process * UNPREDICTABLE operations must not halt or hang the processor UNPRED, used to describe the default state of registers, should be taken as meaning UNPREDICATABLE. A.2.1.2 Undefined UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED operations or behavior may cause data loss. UNDEFINED operations or behavior has one implementation restriction: * UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which there is no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state.
A.2.2
Register Fields
In general, fields marked as reserved should be considered UNPREDICTABLE. In other words, these fields should be written zeros and ignored on a read to preserve future compatibility.
262
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
A.3
A.3.1
* IrDA
Differences between AU1500TM and Au1000TM Processors
Peripherals
The AU1500 processor does not have the following peripherals that are present on the Au1000 processor:
* UART1 * UART2 * SSI * I2S The AU1500 processor has added these functions not present on the Au1000 processor: * PCI 2.2 compliant interface * General Purpose I/O (GPIO): 39 total, 22 dedicated. (Au1000 has 32 total, 5 dedicated.)
A.3.2
Miscellaneous
The NIC base address has changed from 0x0 1050 0000 to 0x0 1150 0000. Some inputs to the interrupt controller have changed due to the addition/removal of blocks. Refer to the interrupt controller section for the AU1500 processor interrupt map. A new CCA encoding has been added to the AU1500 processor. If CCA == 4, all system bus accesses will be cacheline aligned (i.e., no cacheline wrapping is supported). When the PCI Cacheable Memory space is used, it must be mapped to CCA == 4. JTAG memory overlay of the PCI boot memory is not supported.
AMD AlchemyTM AU1500TM Processor Data Book
263
www..com
30361D Support Documentation
A.4
Data Book Revision History
This document is a report of the revision/creation process of the data book for the AU1500 processor. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below.
Table A-5. Revision History
Revision (Date) A B C (June 2005) D (March 2006) Reformatted to bring page count down and correct some minor errors. See Table A-6 for details. Description See the AMD AlchemyTM AU1500TM Processor Specification Update (publication ID 27362).
Table A-6. Edits to Current Revision
Section All Sections / General Revisions / Comments * Reformatted document for page, figure, table and section titles. -- All registers now have either a Heading 3 or 4 associated with it so the electronic PDF will be more useful. * Changed active low signals to use "#" instead of an overbar (e.g., ACRST changed to ACRST#). * Omitted Index and added back cover page. * Removed "Preliminary" mark. Section 1.0 "Overview" * Figure 1-1 "Block Diagram" on page 13: -- Changed pages (moved forward to first page of Section 1.0). * Section 1.2 "Features" on page 14: -- - Modified second bullet under HIgh-Bandwidth Memory Buses (removed "with NAND/NOR Flash support"). * Moved what was Section 1.3 "Data Book Notations" and Section 1.4 "Differences between AU1500TM and Au1000TM Processors" in rev c to the Appendix, Sections A.2 and A.3, respectively. Section 5.0 "DMA Controller" * Table 5-1 "DMA Channel Base Addresses" on page 87: -- Corrected cell heading from "KSEG0" to "KSEG1". * Section 5.1.4 "DMA Channel Buffer Size Registers" on page 92: -- PDF of rev C was messed up and could not be read. Fixed. Section 8.0 "System Control" * Section 8.4.4 "Device Power Management - Sleep" on page 174: -- In the second list of steps, corrected physical address in step 2 (i.e., changed from "0x1FC0_0000 to "0x0 1FC0 0000". * Section 8.3.1.1 "Pin Function" on page 168: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR# in bit 7. Section 9.0 "Power-up, Reset and Boot" * Section 9.3 "Boot" on page 182: -- Corrected the way KSEG1 and Physical addresses were called out (i.e., changed "0xBFC0_0000" to "0xBFC0 0000" and "0x1FC0_0000" to "0x0 1FC0 0000".
264
AMD AlchemyTM AU1500TM Processor Data Book
www..com
Support Documentation 30361D
Table A-6. Edits to Current Revision
Section Section 11.0 "Signal Descriptions" Revisions / Comments * Section 11.0 "Signal Descriptions" on page 200: -- Modified "Note" to reflect use of "#" instead of "overbar" to indicate active low signal. * Figure 11-1 "External Signals" on page 201: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Table 11-3 "Signal Description", "UART3" on page 207: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Table 11-3 "Signal Description", "GPIO" on page 210: -- Added active low designator to UART3 signals mentioned in GPIO9 (U3CTS#), GPIO10 (U3DSR#), GPIO11 (U3DCD#), GPIO12 (U3RI#), GPIO13 (U3RTS#), and GPIO14 (U3DTR#). Section 12.0 "Electrical and Thermal Specifications" Section 13.0 "Packaging, Pin Assignments, and Ordering Information" * Table 12-1 "Absolute Maximum Ratings" on page 216: -- Updated table to reflect TCASE Commercial and TCASE Industrial. * Section 12.5.1 "Power and Voltage for 333, 400, and 500 MHz Rated Parts" on page 218: -- This section was three sections (one section for each part), combined into one section. * Figure 13-2 "Connection Diagram--Top View" on page 240: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Table 13-1 "Pin Assignment -- Sorted by Pin Number" on page 242: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Table 13-2 "Pin Assignment -- Sorted Alphabetically by Default Signal" on page 248: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Table 13-3 "Pin Assignment -- Alternate Signals Sorted Alphabetically" on page 253: -- Added active low designator to UART3 signals U3CTS#, U3DSR#, U3DCD#, U3RI#, U3RTS#, U3DTR#. * Figure 13-3 "OPN Example" and Table 13-4 "Valid OPN Combinations" on page 254: -- Updated to reflect TCASE instead of TA in the Temperature Range description. -- Added Commerical and Industrial Pb-Free data.
AMD AlchemyTM AU1500TM Processor Data Book
265
www..com
www.amd.com
One AMD Place * P.O. Box 3453 * Sunnyvale, CA 94088-3453 USA * Tel: 408-749-4000 or 800-538-8450 * TWX: 910-339-9280 * TELEX: 34-6306

▲Up To Search▲

Price & Availability of AU1500

	To Download AU1500 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .